ATMEGA16A-AU：高效能AVR微控制器学习入门

需积分: 9 55 浏览量更新于2024-07-21 1 收藏 5.31MB PDF 举报

ATMEGA16A-AU是一款高性能、低功耗的AVR 8位微控制器，是入门学习AVR技术的理想选择。它采用先进的RISC架构，具有131种强大的指令，其中大部分可以在单个时钟周期内执行，这显著提高了处理效率。这款微控制器拥有32个8位通用工作寄存器，支持全静态操作，即使在16MHz频率下也能达到高达16MIPS的处理性能。存储方面，ATMEGA16A-AU提供了高耐用性非易失性内存。它内置16KB的In-System Self-programmable Flash程序存储器，可实现自编程，方便在系统内更新或配置。此外，还有512字节的EEPROM用于存储用户数据，以及1KB的内部SRAM，保证了程序运行时的数据暂存能力。值得注意的是，这些非易失性存储器具有极高的写/擦除循环次数，Flash为10,000次，EEPROM为100,000次，数据在85°C下可保持20年，25°C下可达100年。为了增强安全性，该芯片还配备了可独立锁定的可选Boot Code区域，支持真读写操作，可以通过编程锁定机制保护软件免受未经授权的修改。集成的JTAG接口符合IEEE 1149.1标准，支持边界扫描功能，使得调试过程更为便捷。通过JTAG接口，用户可以轻松地对Flash、EEPROM、熔丝和锁位进行编程。在定时器和计数器方面，ATMEGA16A-AU拥有两个8位定时器/计数器，每个都配备独立的预分频器和比较模式，以及一个16位定时器/计数器，具备预分频器、比较模式和捕获模式，这对于实现精确的时间管理和触发事件非常关键。同时，还有一个实时计数器，为实时应用提供了基础的计数和时间测量功能。 ATMEGA16A-AU凭借其高效能、丰富的存储选项、强大的编程灵活性和全面的调试支持，为初学者和专业开发人员提供了卓越的平台，无论是嵌入式系统设计还是简单的微控制器应用，都是一个强大的工具。

8154B–AVR–07/09

ATmega16A

7. AVR Memories

7.1 Overview

This section describes the different memories in the ATmega16A. The AVR architecture has two

main memory spaces, the Data Memory and the Program Memory space. In addition, the

ATmega16A features an EEPROM Memory for data storage. All three memory spaces are linear

and regular.

7.2 In-System Reprogrammable Flash Program Memory

The ATmega16A contains 16K bytes On-chip In-System Reprogrammable Flash memory for

program storage. Since all AVR instructions are 16 or 32 bits wide, the Flash is organized as 8K

x 16. For software security, the Flash Program memory space is divided into two sections, Boot

Program section and Application Program section.

The Flash memory has an endurance of at least 10,000 write/erase cycles. The ATmega16A

Program Counter (PC) is 13 bits wide, thus addressing the 8K program memory locations. The

operation of Boot Program section and associated Boot Lock bits for software protection are

described in detail in “Boot Loader Support – Read-While-Write Self-Programming” on page

250. “Memory Programming” on page 264 contains a detailed description on Flash data serial

downloading using the SPI pins or the JTAG interface.

Constant tables can be allocated within the entire program memory address space (see the LPM

– Load Program Memory Instruction Description).

Timing diagrams for instruction fetch and execution are presented in “Instruction Execution Tim-

ing” on page 13.

Figure 7-1. Program Memory Map

$0000

$1FFF

Application Flash Section

Boot Flash Section

8154B–AVR–07/09

ATmega16A

Figure 7-3. On-chip Data SRAM Access Cycles

7.4 EEPROM Data Memory

The ATmega16A contains 512 bytes of data EEPROM memory. It is organized as a separate

data space, in which single bytes can be read and written. The EEPROM has an endurance of at

least 100,000 write/erase cycles. The access between the EEPROM and the CPU is described

in the following, specifying the EEPROM Address Registers, the EEPROM Data Register, and

the EEPROM Control Register.

For a detailed description of SPI, JTAG, and Parallel data downloading to the EEPROM, see

page 276, page 280, and page 267, respectively.

7.4.1 EEPROM Read/Write Access

The EEPROM Access Registers are accessible in the I/O space.

The write access time for the EEPROM is given in Table 7-1. A self-timing function, however,

lets the user software detect when the next byte can be written. If the user code contains instruc-

tions that write the EEPROM, some precautions must be taken. In heavily filtered power

supplies, V

is likely to rise or fall slowly on Power-up/down. This causes the device for some

period of time to run at a voltage lower than specified as minimum for the clock frequency used.

See “Preventing EEPROM Corruption” on page 19 for details on how to avoid problems in these

situations.

In order to prevent unintentional EEPROM writes, a specific write procedure must be followed.

Refer to the description of the EEPROM Control Register for details on this.

When the EEPROM is read, the CPU is halted for four clock cycles before the next instruction is

executed. When the EEPROM is written, the CPU is halted for two clock cycles before the next

instruction is executed.

7.4.2 EEPROM Write During Power-down Sleep Mode

When entering Power-down Sleep mode while an EEPROM write operation is active, the

EEPROM write operation will continue, and will complete before the Write Access time has

passed. However, when the write operation is completed, the Oscillator continues running, and

clk

Data

Address

Address Valid

T1 T2 T3

Compute Address

Read

Write

CPU

Memory Access Instruction

Next Instruction

8154B–AVR–07/09

ATmega16A

as a consequence, the device does not enter Power-down entirely. It is therefore recommended

to verify that the EEPROM write operation is completed before entering Power-down.

7.4.3 Preventing EEPROM Corruption

During periods of low V

CC,

the EEPROM data can be corrupted because the supply voltage is

too low for the CPU and the EEPROM to operate properly. These issues are the same as for

board level systems using EEPROM, and the same design solutions should be applied.

An EEPROM data corruption can be caused by two situations when the voltage is too low. First,

a regular write sequence to the EEPROM requires a minimum voltage to operate correctly. Sec-

ondly, the CPU itself can execute instructions incorrectly, if the supply voltage is too low.

EEPROM data corruption can easily be avoided by following this design recommendation:

Keep the AVR RESET active (low) during periods of insufficient power supply voltage. This

can be done by enabling the internal Brown-out Detector (BOD). If the detection level of the

internal BOD does not match the needed detection level, an external low V

Reset Protec-

tion circuit can be used. If a reset occurs while a write operation is in progress, the write

operation will be completed provided that the power supply voltage is sufficient.

7.5 I/O Memory

The I/O space definition of the ATmega16A is shown in “Register Summary” on page 334.

All ATmega16A I/Os and peripherals are placed in the I/O space. The I/O locations are

accessed by the IN and OUT instructions, transferring data between the 32 general purpose

working registers and the I/O space. I/O Registers within the address range $00 - $1F are

directly bit-accessible using the SBI and CBI instructions. In these registers, the value of single

bits can be checked by using the SBIS and SBIC instructions. Refer to the Instruction Set sec-

tion for more details. When using the I/O specific commands IN and OUT, the I/O addresses $00

- $3F must be used. When addressing I/O Registers as data space using LD and ST instruc-

tions, $20 must be added to these addresses.

For compatibility with future devices, reserved bits should be written to zero if accessed.

Reserved I/O memory addresses should never be written.

Some of the Status Flags are cleared by writing a logical one to them. Note that the CBI and SBI

instructions will operate on all bits in the I/O Register, writing a one back into any flag read as

set, thus clearing the flag. The CBI and SBI instructions work with registers $00 to $1F only.

The I/O and Peripherals Control Registers are explained in later sections.

7.6 Register Description

7.6.1 EEARH and EEARL – The EEPROM Address Register

Bit 151413121110 9 8

–––––––EEAR8EEARH

EEAR7 EEAR6 EEAR5 EEAR4 EEAR3 EEAR2 EEAR1 EEAR0 EEARL

76543210

Read/Write RRRRRRRR/W

R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value 0 0 0 0 0 0 0 X

XXXXXXXX

8154B–AVR–07/09

ATmega16A

• Bits 15:9 – Res: Reserved Bits

These bits are reserved bits in the ATmega16A and will always read as zero.

• Bits 8:0 – EEAR8:0: EEPROM Address

The EEPROM Address Registers

– EEARH and EEARL – specify the EEPROM address in the

512 bytes EEPROM space. The EEPROM data bytes are addressed linearly between 0 and

511. The initial value of EEAR is undefined. A proper value must be written before the EEPROM

may be accessed.

7.6.2 EEDR – The EEPROM Data Register

• Bits 7:0 – EEDR7.0: EEPROM Data

For the EEPROM write operation, the EEDR Register contains the data to be written to the

EEPROM in the address given by the EEAR Register. For the EEPROM read operation, the

EEDR contains the data read out from the EEPROM at the address given by EEAR.

7.6.3 EECR – The EEPROM Control Register

• Bits 7:4 – Res: Reserved Bits

These bits are reserved bits in the ATmega16A and will always read as zero.

• Bit 3 – EERIE: EEPROM Ready Interrupt Enable

Writing EERIE to one enables the EEPROM Ready Interrupt if the I bit in SREG is set. Writing

EERIE to zero disables the interrupt. The EEPROM Ready interrupt generates a constant inter-

rupt when EEWE is cleared.

• Bit 2 – EEMWE: EEPROM Master Write Enable

The EEMWE bit determines whether setting EEWE to one causes the EEPROM to be written.

When EEMWE is set, setting EEWE within four clock cycles will write data to the EEPROM at

the selected address If EEMWE is zero, setting EEWE will have no effect. When EEMWE has

been written to one by software, hardware clears the bit to zero after four clock cycles. See the

description of the EEWE bit for an EEPROM write procedure.

• Bit 1 – EEWE: EEPROM Write Enable

The EEPROM Write Enable Signal EEWE is the write strobe to the EEPROM. When address

and data are correctly set up, the EEWE bit must be written to one to write the value into the

EEPROM. The EEMWE bit must be written to one before a logical one is written to EEWE, oth-

erwise no EEPROM write takes place. The following procedure should be followed when writing

the EEPROM (the order of steps 3 and 4 is not essential):

Bit 76543210

MSB LSB EEDR

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value 0 0 0 0 0 0 0 0

Bit 76543210

– – – – EERIE EEMWE EEWE EERE EECR

Read/Write RRRRR/WR/WR/WR/W

Initial Value000000X0

剩余352页未读，继续阅读

千叶择木

粉丝: 6
资源: 3

ATMEGA16A-AU：高效能AVR微控制器学习入门

Atmega16引脚图

Atmega16a/Atmega32U4单片机原理图封装库（AD库）

ATMEGA16A-PU中文资料

ATMEGA328P-AU.rar_ATMEGA328-AU_atmega328p_datasheet

ATMEGA16A-PU微控制器技术特性详解

ATMEGA8A-AU

SPI.zip_ATmega64A-AU

ATMEGA8A资料,ATMEGA8A-AU规格书,MEGA8新版本

TQFP32封装0.8mm间距 For Atmega8a-AU

AVR微控制器ATMEGA16A-PU：高性能低功耗特性详解

最新资源