24XX256芯片系列：低功耗、高性能的串行EEPROM

20001203U

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"芯片手册2000" 本文档主要介绍了Microchip Technology Inc.生产的24AA256、24LC256和24FC256这三款256Kbit串行电可擦除只读存储器（EEPROM）芯片。这些芯片在设计上具有高度的技术先进性和低功耗特性，适用于多种电子设备和系统。 1. **电源兼容性与低功耗** - 24AA256和24FC256器件可在低至1.7V的单电源下工作，而24LC256器件则需2.5V。 - 在5.5V电压和400kHz的工作频率下，读取电流最大为400uA，这确保了高效能的同时降低了能耗。 - 待机状态下，电流消耗仅为1uA最大，即使在3.6V电压下也能保持极低的功耗。 2. **2-Wire Serial Interface (I2C 兼容)** - 这些器件采用2线串行接口，与I2C协议兼容，允许在有限的引脚数下实现多个设备的级联，提高了系统设计的灵活性。 3. **噪声抑制与输出控制** - Schmitt触发输入设计用于增强抗噪声能力，确保数据传输的稳定性。 - 输出斜率控制功能可以消除地线反弹，进一步提高系统的稳定性。 4. **时钟兼容性和快速写入** - 支持100kHz和400kHz的时钟频率，满足不同应用需求。 - 页面写入时间最大为5ms，实现了快速的数据写入操作。 5. **自定时擦除/写入周期** - 内置的自我定时擦除/写入循环，简化了编程流程，用户无需额外的时序控制。 6. **硬件写保护** - 提供硬件写保护功能，保护重要数据免受意外修改。 7. **耐用性与数据保留** - 超过一百万次的擦写周期，确保了芯片的长期可靠性。 - 数据保留时间超过200年，保证了存储数据的长期有效性。 8. **封装选项与环境适应性** - 提供8引脚PDIP、SOIC、SOIJ、DFN、TDFN、TSSOP和MSOP等多种封装形式，以适应不同应用场合。 - 符合RoHS标准，环保且无铅。 - 设计有多种温度范围版本，满足不同环境条件下的使用要求。 24AA256、24LC256和24FC256是适用于各种低功耗、高可靠性的嵌入式系统和设备的理想存储解决方案，尤其适合于需要长期数据保存和频繁写入操作的应用场景。

24AA256/24LC256/24FC256

DS20001203U-page 8  1998-2013 Microchip Technology Inc.

5.0 DEVICE ADDRESSING

A control byte is the first byte received following the

Start condition from the master device (Figure 5-1).

The control byte consists of a 4-bit control code. For the

24XX256, this is set as ‘

1010’ binary for read and

write operations. The next three bits of the control byte

are the Chip Select bits (A2, A1, A0). The Chip Select

bits allow the use of up to eight 24XX256 devices on

the same bus and are used to select which device is

accessed. The Chip Select bits in the control byte must

correspond to the logic levels on the corresponding A2,

A1 and A0 pins for the device to respond. These bits

are, in effect, the three Most Significant bits of the word

address.

For the MSOP package, the A0 and A1 pins are not

connected. During device addressing, the A0 and A1

Chip Select bits (Figures 5-1 and 5-2) should be set to

‘0’. Only two 24XX256 MSOP packages can be

connected to the same bus.

The last bit of the control byte defines the operation to

be performed. When set to a one, a read operation is

selected. When set to a zero, a write operation is

selected. The next two bytes received define the

address of the first data byte (Figure 5-2). Because

only A14…A0 are used, the upper address bits are a

“don’t care.” The upper address bits are transferred

first, followed by the Less Significant bits.

Following the Start condition, the 24XX256 monitors

the SDA bus checking the device type identifier being

transmitted. Upon receiving a ‘

1010’ code and

appropriate device select bits, the slave device outputs

an Acknowledge signal on the SDA line. Depending on

the state of the R/W

bit, the 24XX256 will select a read

or write operation.

FIGURE 5-1: CONTROL BYTE

FORMAT

5.1 Contiguous Addressing Across

Multiple Devices

The Chip Select bits A2, A1 and A0 can be used to

expand the contiguous address space for up to 2 Mbit

by adding up to eight 24XX256 devices on the same

bus. In this case, software can use A0 of the control

byte as address bit A15; A1 as address bit A16; and A2

as address bit A17. It is not possible to sequentially

read across device boundaries.

For the MSOP package, up to two 24XX256 devices

can be added for up to 512 Kbit of address space. In

this case, software can use A2 of the control byte as

address bit A17. Bits A0 (A15) and A1 (A16) of the

control byte must always be set to a logic ‘0’ for the

MSOP.

FIGURE 5-2: ADDRESS SEQUENCE BIT ASSIGNMENTS

0 A2 A1 A0

ACKR/W

Control Code

Chip Select

Bits

Slave Address

Acknowledge Bit

Start Bit

Read/Write

Bit

1 010

R/W x

••••••

Control Byte Address High Byte Address Low Byte

Control

Code

Chip

Select

Bits

x = “don’t care” bit

 1998-2013 Microchip Technology Inc. DS20001203U-page 9

24AA256/24LC256/24FC256

6.0 WRITE OPERATIONS

6.1 Byte Write

Following the Start condition from the master, the

control code (four bits), the Chip Select (three bits) and

the R/W bit (which is a logic low) are clocked onto the

bus by the master transmitter. This indicates to the

addressed slave receiver that the address high byte will

follow after it has generated an Acknowledge bit during

the ninth clock cycle. Therefore, the next byte

transmitted by the master is the high-order byte of the

word address and will be written into the Address

Pointer of the 24XX256. The next byte is the Least

Significant Address Byte. After receiving another

Acknowledge signal from the 24XX256, the master

device will transmit the data word to be written into the

addressed memory location. The 24XX256 acknowl-

edges again and the master generates a Stop

condition. This initiates the internal write cycle and

during this time, the 24XX256 will not generate

Acknowledge signals (Figure 6-1). If an attempt is

made to write to the array with the WP pin held high, the

device will acknowledge the command but no write

cycle will occur, no data will be written, and the device

will immediately accept a new command. After a byte

Write command, the internal address counter will point

to the address location following the one that was just

written.

6.2 Page Write

The write control byte, word address and the first data

byte are transmitted to the 24XX256 in much the same

way as in a byte write. The exception is that instead of

generating a Stop condition, the master transmits up to

63 additional bytes, which are temporarily stored in the

on-chip page buffer, and will be written into memory

once the master has transmitted a Stop condition.

Upon receipt of each word, the six lower Address

Pointer bits are internally incremented by one. If the

master should transmit more than 64 bytes prior to

generating the Stop condition, the address counter will

roll over and the previously received data will be over-

written. As with the byte write operation, once the Stop

condition is received, an internal write cycle will begin

(Figure 6-2). If an attempt is made to write to the array

with the WP pin held high, the device will acknowledge

the command, but no write cycle will occur, no data will

be written and the device will immediately accept a new

command.

6.3 Write Protection

The WP pin allows the user to write-protect the entire

array (0000-7FFF) when the pin is tied to V

CC. If tied to

SS the write protection is disabled. The WP pin is

sampled at the Stop bit for every Write command

(Figure 1-1). Toggling the WP pin after the Stop bit will

have no effect on the execution of the write cycle.

Note: When doing a write of less than 64 bytes

the data in the rest of the page is

refreshed along with the data bytes being

written. This will force the entire page to

endure a write cycle, for this reason

endurance is specified per page.

Note: Page write operations are limited to

writing bytes within a single physical page,

regardless of the number of bytes

actually being written. Physical page

boundaries start at addresses that are

integer multiples of the page buffer size

(or ‘page size’) and end at addresses that

are integer multiples of [page size – 1]. If

a Page Write command attempts to write

across a physical page boundary, the

result is that the data wraps around to the

beginning of the current page (overwriting

data previously stored there), instead of

being written to the next page, as might be

expected. It is, therefore, necessary for

the application software to prevent page

write operations that would attempt to

cross a page boundary.

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