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MPC5744P芯片手册:架构与功能详解
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本资源是关于MPC5744P芯片的手册,由NXPSemiconductors发布,版本为Rev.6,日期为2016年6月。MPC5744P是一款多功能微控制器(MCU),适用于多种应用领域,支持MPC5744P、MPC5743P、MPC5742P和MPC5741P等系列。手册详尽介绍了该芯片的特性、架构、内存结构以及外围设备。
**1. 芯片概述**
- **总体架构**: 手册首先提供了MPC5744P的整体架构介绍,包括核心模块、内存系统和外设通信,以帮助用户理解芯片的工作原理。
- **核心功能**: 芯片具备软件调试和校准功能,这有助于开发者进行高效的应用程序开发和调试工作。
- **内存层次结构**: 内存设计包括系统级SRAM和处理器内核本地SRAM,这支持高效的数据处理和存储需求。
**2. 应用与兼容性**
- **目标应用**: 手册列举了MPC5744P适用于的典型应用,如嵌入式系统、工业控制和物联网等领域。
- **兼容性**: 与MPC5643L的兼容性被特别强调,表明这款芯片可以替代或扩展MPC5643L在某些项目中的性能。
**3. 详细规格**
- **嵌入式内存**: 章节深入探讨了芯片的存储器部分,包括系统级SRAM的容量、速度和用途,以及处理器内核本地SRAM的特性,这对于内存管理至关重要。
- **I/O控制**: 提供了关于如何管理和控制芯片的输入输出端口的信息,这是连接外部设备和实现系统通信的关键部分。
**4. 特殊术语与缩略词**
- 手册还定义了一些特定的术语和缩写,以便于读者理解和参考,确保他们在阅读时对专业词汇有清晰的理解。
**总结**
通过阅读这份MPC5744P Reference Manual Rev.6,用户能够全面了解该芯片的功能、性能参数、编程接口和设计指南,这对于硬件工程师、嵌入式开发人员和系统集成者来说是一份重要的参考资料。无论是进行新项目设计还是对现有系统进行升级,这份文档都能提供所需的技术支持。
Section number Title Page
21.5.7 INTC Monitor Mode Register 0 (INTC_MMRC0)..................................................................................... 609
21.5.8
INTC HIPRI Register (INTC_HIPRInC0).................................................................................................. 610
21.5.9
INTC LAT Register (INTC_LATnC0)........................................................................................................611
21.5.10
INTC Timer Register (INTC_TIMERnC0)................................................................................................. 611
21.6 Functional description...................................................................................................................................................612
21.6.1 Interrupt request sources.............................................................................................................................. 612
21.6.2 Priority management....................................................................................................................................613
21.6.3 Handshaking with processor........................................................................................................................ 615
21.6.4 Interrupt Controller Monitor (INTCM)........................................................................................................618
21.7 Initialization/application information........................................................................................................................... 619
21.7.1 Initialization flow.........................................................................................................................................619
21.7.2 Interrupt exception handler.......................................................................................................................... 620
21.7.3 ISR, RTOS, and task hierarchy....................................................................................................................621
21.7.4 Order of execution....................................................................................................................................... 622
21.7.5 Priority ceiling protocol............................................................................................................................... 623
21.7.6 Selecting priorities according to request rates and deadlines...................................................................... 626
21.7.7 Software-settable interrupt requests.............................................................................................................627
21.7.8 Lowering priority within an ISR..................................................................................................................628
21.7.9 Negating an interrupt request outside of its ISR..........................................................................................629
21.7.10 Examining LIFO contents............................................................................................................................629
21.8 Interrupt sources............................................................................................................................................................630
Chapter 22
Enhanced Direct Memory Access (eDMA)
22.1 Introduction...................................................................................................................................................................631
22.1.1 eDMA system block diagram...................................................................................................................... 631
22.1.2 Block parts................................................................................................................................................... 632
22.1.3 Features........................................................................................................................................................ 633
22.2 Modes of operation....................................................................................................................................................... 634
22.3 Memory map/register definition................................................................................................................................... 635
MPC5744P Reference Manual, Rev. 6, 06/2016
16 NXP Semiconductors
Section number Title Page
22.3.1 TCD memory............................................................................................................................................... 635
22.3.2 TCD initialization........................................................................................................................................ 635
22.3.3 TCD structure...............................................................................................................................................635
22.3.4 Reserved memory and bit fields...................................................................................................................636
22.3.1 Control Register (DMA_CR).......................................................................................................................663
22.3.2 Error Status Register (DMA_ES)................................................................................................................ 666
22.3.3 Enable Request Register (DMA_ERQ)....................................................................................................... 669
22.3.4 Enable Error Interrupt Register (DMA_EEI)...............................................................................................672
22.3.5 Set Enable Request Register (DMA_SERQ)...............................................................................................676
22.3.6 Clear Enable Request Register (DMA_CERQ)...........................................................................................677
22.3.7 Set Enable Error Interrupt Register (DMA_SEEI)...................................................................................... 678
22.3.8 Clear Enable Error Interrupt Register (DMA_CEEI).................................................................................. 679
22.3.9 Clear Interrupt Request Register (DMA_CINT)......................................................................................... 680
22.3.10 Clear Error Register (DMA_CERR)............................................................................................................681
22.3.11 Set START Bit Register (DMA_SSRT)...................................................................................................... 682
22.3.12 Clear DONE Status Bit Register (DMA_CDNE)........................................................................................683
22.3.13 Interrupt Request Register (DMA_INT)......................................................................................................684
22.3.14 Error Register (DMA_ERR)........................................................................................................................ 687
22.3.15 Hardware Request Status Register (DMA_HRS)........................................................................................ 691
22.3.16
Channel n Priority Register (DMA_DCHPRIn).......................................................................................... 697
22.3.17
Channel n Master ID Register (DMA_DCHMIDn).................................................................................... 698
22.3.18
TCD Source Address (DMA_TCDn_SADDR)...........................................................................................699
22.3.19
TCD Transfer Attributes (DMA_TCDn_ATTR).........................................................................................699
22.3.20
TCD Signed Source Address Offset (DMA_TCDn_SOFF)........................................................................700
22.3.21
TCD Minor Byte Count (Minor Loop Mapping Disabled) (DMA_TCDn_NBYTES_MLNO)................. 701
22.3.22 TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled)
(DMA_TCDn_NBYTES_MLOFFNO).......................................................................................................701
22.3.23 TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled)
(DMA_TCDn_NBYTES_MLOFFYES)..................................................................................................... 703
MPC5744P Reference Manual, Rev. 6, 06/2016
NXP Semiconductors 17
Section number Title Page
22.3.24
TCD Last Source Address Adjustment (DMA_TCDn_SLAST).................................................................704
22.3.25
TCD Destination Address (DMA_TCDn_DADDR)...................................................................................704
22.3.26 TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled)
(DMA_TCDn_CITER_ELINKYES)...........................................................................................................705
22.3.27 TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled)
(DMA_TCDn_CITER_ELINKNO)............................................................................................................ 706
22.3.28
TCD Signed Destination Address Offset (DMA_TCDn_DOFF)................................................................707
22.3.29
TCD Last Destination Address Adjustment/Scatter Gather Address (DMA_TCDn_DLASTSGA).......... 707
22.3.30 TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled)
(DMA_TCDn_BITER_ELINKYES)...........................................................................................................708
22.3.31 TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled)
(DMA_TCDn_BITER_ELINKNO)............................................................................................................ 709
22.3.32
TCD Control and Status (DMA_TCDn_CSR)............................................................................................ 710
22.4 Functional description...................................................................................................................................................712
22.4.1 eDMA basic data flow................................................................................................................................. 712
22.4.2 Fault reporting and handling........................................................................................................................715
22.4.3 Channel preemption..................................................................................................................................... 718
22.4.4 Performance................................................................................................................................................. 718
22.5 Initialization/application information........................................................................................................................... 722
22.5.1 eDMA initialization..................................................................................................................................... 722
22.5.2 Programming errors..................................................................................................................................... 724
22.5.3 Arbitration mode considerations..................................................................................................................725
22.5.4 Performing DMA transfers.......................................................................................................................... 726
22.5.5 Monitoring transfer descriptor status........................................................................................................... 730
22.5.6 Channel Linking...........................................................................................................................................732
22.5.7 Dynamic programming................................................................................................................................ 733
Chapter 23
Direct Memory Access Multiplexer (DMAMUX)
23.1 Introduction...................................................................................................................................................................739
23.1.1 Overview......................................................................................................................................................739
MPC5744P Reference Manual, Rev. 6, 06/2016
18 NXP Semiconductors
Section number Title Page
23.1.2 Features........................................................................................................................................................ 740
23.1.3 Modes of operation...................................................................................................................................... 740
23.2 External signal description............................................................................................................................................741
23.3 Memory map/register definition................................................................................................................................... 741
23.3.1
Channel Configuration register (DMAMUX_CHCFGn)............................................................................ 742
23.4 Functional description...................................................................................................................................................743
23.4.1 DMA channels with periodic triggering capability......................................................................................743
23.4.2 DMA channels with no triggering capability...............................................................................................745
23.4.3 Always-enabled DMA sources.................................................................................................................... 746
23.5 Initialization/application information........................................................................................................................... 747
23.5.1 Reset.............................................................................................................................................................747
23.5.2 Enabling and configuring sources................................................................................................................747
Chapter 24
Error Injection Module (EIM)
24.1 Introduction...................................................................................................................................................................751
24.1.1 Overview......................................................................................................................................................751
24.1.2 Features........................................................................................................................................................ 752
24.2 Memory map and register definition.............................................................................................................................753
24.2.1 Error Injection Module Configuration Register (EIM_EIMCR)................................................................. 754
24.2.2 Error Injection Channel Enable register (EIM_EICHEN)...........................................................................755
24.2.3
Error Injection Channel Descriptor, Word0 (EIM_EICHDn_WORD0)..................................................... 756
24.2.4
Error Injection Channel Descriptor, Word1 (EIM_EICHDn_WORD1)..................................................... 757
24.2.5
Error Injection Channel Descriptor, Word2 (EIM_EICHDn_WORD2)..................................................... 757
24.3 Functional description...................................................................................................................................................758
Chapter 25
Dual PLL Digital Interface (PLLDIG)
25.1 Introduction...................................................................................................................................................................759
25.2 Block Diagram..............................................................................................................................................................759
25.3 Features.........................................................................................................................................................................759
MPC5744P Reference Manual, Rev. 6, 06/2016
NXP Semiconductors 19
Section number Title Page
25.4 Modes of operation....................................................................................................................................................... 760
25.4.1 Normal mode with reference, PLL0 or both PLLs enabled.........................................................................760
25.5 Memory map and register definition.............................................................................................................................761
25.5.1 PLLDIG PLL0 Control Register (PLLDIG_PLL0CR)............................................................................... 762
25.5.2 PLLDIG PLL0 Status Register (PLLDIG_PLL0SR).................................................................................. 764
25.5.3 PLLDIG PLL0 Divider Register (PLLDIG_PLL0DV)...............................................................................766
25.5.4 PLLDIG PLL1 Control Register (PLLDIG_PLL1CR)............................................................................... 768
25.5.5 PLLDIG PLL1 Status Register (PLLDIG_PLL1SR).................................................................................. 770
25.5.6 PLLDIG PLL1 Divider Register (PLLDIG_PLL1DV)...............................................................................771
25.5.7 PLLDIG PLL1 Frequency Modulation Register (PLLDIG_PLL1FM).......................................................773
25.5.8 PLLDIG PLL1 Fractional Divide Register (PLLDIG_PLL1FD)................................................................775
25.6 Register classification for safety requirements.............................................................................................................776
25.7 Functional description...................................................................................................................................................776
25.7.1 Input clock frequency...................................................................................................................................776
25.7.2 Clock configuration......................................................................................................................................776
25.7.3 Loss of lock..................................................................................................................................................778
25.7.4 Frequency modulation..................................................................................................................................778
25.8 Initialization information.............................................................................................................................................. 780
Chapter 26
Clock Monitor Unit (CMU)
26.1 Introduction...................................................................................................................................................................781
26.1.1 Main features................................................................................................................................................782
26.2 Block diagram...............................................................................................................................................................782
26.3 Signals...........................................................................................................................................................................782
26.4 Register description and memory map......................................................................................................................... 783
26.4.1 CMU Control Status Register (CMU_CSR)................................................................................................784
26.4.2 CMU Frequency Display Register (CMU_FDR)........................................................................................ 785
26.4.3 CMU High Frequency Reference Register CLKMN1 (CMU_HFREFR)...................................................786
26.4.4 CMU Low Frequency Reference Register CLKMN1 (CMU_LFREFR)....................................................786
MPC5744P Reference Manual, Rev. 6, 06/2016
20 NXP Semiconductors
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