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Fabrication of Sub-Micrometer-Sized MoS
2
Thin-Film
Transistor by Phase Mode AFM Lithography
Lianqing Liu,* Jialin Shi, Meng Li, Peng Yu, Tie Yang, and Guangyong Li
Prof. L. Liu, Dr. J. Shi, M. Li, P. Yu, T. Yang
State Key Laboratory of Robotics
Shenyang Institute of Automation
Chinese Academy of Science
Shenyang 110016, China
E-mail: lqliu@sia.cn
M. Li
University of Chinese Academy of Science
Beijing 100049, China
Prof. G. Li
Department of Electrical and Computer Engineering
University of Pittsburgh
Pittsburgh, PA 15213, USA
The ORCID identification number(s) for the author(s) of this article
can be found under https://doi.org/10.1002/smll.201803273.
DOI: 10.1002/smll.201803273
to ensure the alignment accuracy, the
size shrinking of target 2DMs is limited
at a few to tens of microns in the devices
fabrication process. Besides, the damage
or contamination caused by high-energy
exposure has a distinct impact on the per-
formance of 2DMs devices.
[12]
Atomic force microscopy (AFM) lithog-
raphy, using a nano-tip as both imaging
and scratching tool, can read topography
with sub-nanometer sensitivity without
causing exposure of the resist. With the
advantages of being relatively low cost,
having a high level of flexibility on mate-
rial compatibility and capability of opera-
tion in ambient conditions,
[13–17]
AFM
lithography is an ideal nanofabrication approach with high
resolution and controllability. In addition, AFM can read
residual topography of objects buried beneath spin-coated
film, which removes the need of reference markers and the
errors of overlay and alignment.
[18,19]
Among AFM lithography
techniques, thermal-scanning probe lithography (t-SPL) and
mechanical scratching with AFM lithography have the potential
to fabricate functional devices based on sub-micrometer-sized
2DMs.
[20,21]
However, the hot tip of t-SPL with the tempera-
ture of ≈600 °C accelerates the oxidation process of 2DMs,
[22]
which leads to the properties changes of 2DMs. AFM lithog-
raphy by mechanical scratching with a sharp tip is no harm
to 2DMs with a relative small scratching force, which is large
enough for pattern polymer resist. Although metal nanowire
and nanodots have successfully been fabricated combining
the mechanical scratching with AFM and lift-off process,
[23,24]
it
still remains a formidable challenge to fabricate large area elec-
tronic pad with an accuracy contact with sub-micrometer-sized
2DMs at nanoscale. Besides, for patterning on the polymer
resist with few to tens nanometers thickness, the over-cut,
under-cut, and severe tip wear are obstacles for the fabrication
of 2DMs devices by AFM mechanical machining method. In
this work, we shrink the planar size of MoS
2
thin-film transis-
tors (TFTs) down to sub-micrometer by fabricating electrodes
aligned on MoS
2
thin film with phase mode AFM lithography,
which eliminates the debris effect and greatly reduces the tip
wear. The produced functional devices based on sub-microm-
eter-sized MoS
2
demonstrate n-type characteristics. It offers a
more flexible and easier way to fabricate the prototype of 2DMs
devices for exploring the performance of 2DMs TFTs or other
device at nanoscale.
The phase mode of AFM lithography, as illustrated in
Figure 1, is different from the conventional force mode by using
the phase response of cantilever as the feedback of the control
The phase mode atomic force microscopy (AFM) lithography and monolayer
lift-off process are combined to fabricate electronics based on 2D materials
(2DMs), which remove the need for pre-fabricating markers and increase the
accuracy of the overlay and alignment. The promising phase mode of AFM
lithography eliminates the drawbacks of the conventional force mode such as
the over-cut, under-cut, debris effect, and severe tip wear. The planar size of
MoS
2
thin-film transistors is shrunken down to sub-micrometer by the pro-
posed method, and the fabricated devices demonstrate n-type characteristics.
It offers a more flexible and easier way to fabricate prototypes of sub-microm-
eter-sized 2DMs based devices, and gives the opportunity to explore the size
effect on the performance of 2DMs devices.
Micro-Nano Fabrication
2D materials (2DMs), with the merits of atomic thickness and
dangling bond-free surface, intrinsically suppressing trap gen-
eration and surface scattering, are considered as the excellent
candidates in replacing and supplementing silicon-based tran-
sistors.
[1–4]
To meet the long-term (2026) expectations of the
ITRS for both high-performance and low-power devices, scaling
down the planar size of 2DMs devices is the urgently needed
and main technological challenge.
[5]
Advances in micro-/nano-
lithography technique, such as electron-beam lithography
(EBL), nanoimprint lithography, laser patterning, photolithog-
raphy, and optically induced electrodeposition, have enabled the
fabrication of 2DMs devices.
[6–10]
To date, EBL is the most frequent fabrication method of
2DMs based devices. In EBL, the overlay of lithography pat-
terns on existing 2DMs is achieved by pre-fabricating dedicated
reference marks.
[11]
The overlay errors caused by marker sizes,
marker degradation, microscopy technique, and separate posi-
tioning system, will lead to errors in the alignment. In order
Small 2018, 14, 1803273