高速采样ADC设计关键：模拟输入驱动与性能优化

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"模拟电路应用4--HIGH SPEED(Analog Devices提供)，主要讨论高速采样ADC在信号处理系统中的应用和设计考虑，包括动态性能、ADC输入保护和钳位、驱动带开关电容输入的ADC、增益设置和电平转换、外部参考电压生成等关键点。" 在现代高速采样ADC的设计中，其目标是实现低失真和宽动态范围的信号处理。然而，实际达到这些性能指标不仅依赖于ADC本身，还需要恰当设计外部支持电路。其中，模拟输入驱动电路尤其关键，因为设计不当可能会降低ADC固有的动态性能。 4.1 ADC动态性能考虑选择驱动放大器时，需要根据ADC的动态性能进行。驱动放大器应能提供稳定且无损的信号，确保ADC在高速采样时保持良好的信噪比和线性度。 4.2 驱动闪存转换器对于闪存型ADC，其输入驱动要求特殊，通常需要快速切换能力和低噪声特性，以适应高采样率和高分辨率的需求。 4.3 驱动AD9050单电源ADC AD9050是一个特定的高速ADC示例，其驱动要求可能包括特定的电源电压、输入信号范围和上升/下降时间限制，设计时需要充分了解这些要求。 4.4 驱动带开关电容输入的ADC 这类ADC的输入电路包含开关电容网络，驱动电路必须提供足够的驱动能力，同时考虑到输入电容的充放电特性，防止产生过冲或下冲。 4.5 增益设置和电平转换为了匹配ADC的输入范围，可能需要调整输入信号的增益或进行电平转换。这可以通过使用运算放大器和其他有源组件来实现，确保信号在ADC的有效输入范围内。 4.6 外部参考电压生成高精度的ADC通常需要稳定的参考电压源，外部生成可以提高系统的总体精度，但也要注意参考电压的噪声和温度漂移对ADC性能的影响。 4.7 ADC输入保护和钳位保护电路用于防止过压或瞬态电压损坏ADC输入，钳位电路则可限制输入电压在安全范围内，确保ADC的可靠工作。 4.8 钳位放大器的应用钳位放大器在抑制噪声和保护ADC输入方面起到关键作用，它们可以在高速采样环境中提供瞬态响应和保护。 4.9 高速采样ADC中的噪声考虑在高速应用中，噪声是不可忽视的因素，包括热噪声、量化噪声和电路噪声等。设计师需要评估并优化整个信号链路的噪声性能，以提高系统的整体信号质量。总结来说，高速采样ADC的应用涉及多方面的设计考虑，从驱动电路的选择到噪声管理，每一个环节都对整体性能产生直接影响。正确理解并处理这些细节，是确保ADC在现代信号处理系统中发挥最大效能的关键。

the high-frequency ENOB of a sampling ADC, and may be more cost-effective than

replacing the ADC with a more expensive one.

It should be noted that there is also a fixed component which makes up the ADC

aperture time. This component, usually called effective aperture delay time, does not

produce an error. It simply results in a time offset between the time the ADC is

asked to sample and when the actual sample takes place (see Figure 4.9). The

variation or tolerance placed on this parameter from part to part is important in

simultaneous sampling applications or other applications such as I and Q

demodulation where several ADCs are required to track each other.

EFFECTIVE APERATURE DELAY TIME

Figure 4.9

The distortion produced by an ADC or DAC cannot be analyzed in terms of second

and third-order intercepts, as in the case of an amplifier. This is because there are

two components of distortion in a high performance data converter. One component

is due to the non-linearity associated with the analog circuits within the converter.

This non-linearity has the familiar "bow" or "s"-shaped curve shown in Figure 4.10.

(It may be polynomial or logarithmic in form). The distortion associated with this

type of non-linearity is sometimes referred to as soft distortion and produces low-

order distortion products. This component of distortion behaves in the traditional

manner, and is a function of signal level. In a practical data converter, however, the

soft distortion is usually much less than the other component of distortion, which is

due to the differential nonlinearity of the transfer function. The converter transfer

function is more likely to have discrete points of discontinuity across the signal

range as shown in Figure 4.10.

FUNCTIONS OF THE ADC DRIVE AMPLIFIER

Buffer the analog signal from the ADC input:

ADC input may not be a constant high impedance

ADC input may generate transient loads

Provide other functions:

Gain

Level Shifting

If the ADC input is constant high impedance with no transient

loading, do not use a buffer amplifier unless required for gain or

level shifting!!

Figure 4.11

The S/(N+D) plot of the ADC should generally be used as the first selection criterion

for the drive amplifier. If the Total Harmonic Distortion Plus Noise (THD+N) of the

drive amplifier is always 6 to 10dB better than the S/(N+D) of the ADC over the

frequency range of interest, then the overall degradation in S/(N+D) caused by the

amplifier will be limited to between approximately 0.5dB and 1db, respectively. This

will be illustrated using two state of the art components: the AD9022 12 bit,

20MSPS ADC and the AD9631 op amp. A block diagram of the AD9022 is shown in

Figure 4.12, and key specifications in Figure 4.13. AD9631/AD9632 key

specifications are given in Figure 4.14.

The AD9022 employs a three-pass subranging architecture and digital error

correction. The analog input is applied to a 300Ω attenuator and passed to the

sampling bridge of the first internal track-and-hold amplifier (T/H). The held value

of the first T/H is applied to a 5-bit flash converter and a second T/H. The 5-bit flash

converter resolves the most significant bits (MSBs) of the held analog voltage. These

5 bits are reconstructed via a 5-bit DAC and subtracted from the original T/H output

signal to form a residue signal. A second T/H holds the amplified residue signal

while it is encoded with a second 5-bit flash ADC. Again, the 5-bits are reconstructed

and subtracted from the second T/H output to form a residue signal. This residue is

amplified and encoded with a 4-bit flash ADC to provide the 3 least significant bits

(LSBs) of the digital output and one bit of error correction. The digital error

correction logic combines the data from the three flash converters and presents the

result as a 12-bit parallel digital word. The output stage is TTL (AD9022), or ECL

(AD9023). Output data can be strobed on the rising edge of the ENCODE command.

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