BCM2711 ARM 外设手册：2020年版 BCM2835 更新与历史

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BCM2711 ARM 外设数据手册详细介绍了博通公司生产的 BCM2711 SoC（系统级芯片）的外围设备特性。这份文档是基于早期 BCM2835 的 ARM 外设文档进行扩展和改进的，旨在为用户和开发者提供全面的技术指南。文档由 Broadcom Europe Ltd. 和 Raspberry Pi Trading Ltd. 共同发布，版权所有，最后更新日期为 2020 年 10 月 16 日，版本为 githash: bfc2f1f 清洁版。历史记录在表 1 中列出了三个主要的发布阶段： 1. 首次发布于 2020 年 2 月 5日，标志着BCM2711 外设的初始公开。 2. 2020年9月24日的更新修正了GPIO基地址，并进行了风格上的优化。 3. 2020年10月16日，正式发布了第一份公共版本。用户在使用这份资料时，需注意法律免责声明，即Raspberry Pi Trading Ltd. 提供的关于 Raspberry Pi 产品的技术及可靠性数据（包括数据手册），均为"按现状"提供，不附带任何明示或默示的质量保证，包括适销性和特定用途的适用性。根据适用法律，Raspberry Pi Trading Ltd. 在任何情况下都不承担因使用这些资源而产生的直接、间接、偶然、特殊或连带损失的责任，除非这些损失是由其明显疏忽或欺诈行为造成。该文档涵盖了BCM2711 SoC的关键外设组件，如GPIO（通用输入输出）控制器、UART（通用串行总线）、SPI（同步串行接口）、I2C（Inter-Integrated Circuit）总线、PWM（脉宽调制）通道、以及GPIO引脚的具体功能和地址分配。此外，还可能包含中断管理、电源管理、时钟配置等高级特性。对于硬件开发者和系统集成者来说，这份文档提供了设计、调试和优化基于BCM2711平台应用的重要参考资料。

Receiver enable

If this bit is clear no new symbols will be accepted by the receiver. Any symbols in progress of reception will be

finished.

Transmitter enable

If this bit is clear no new symbols will be sent by the transmitter. Any symbols in progress of transmission will be

finished.

Auto flow control

Automatic flow control can be enabled independent for the receiver and the transmitter.

CTS auto flow control impacts the transmitter only. The transmitter will not send out new symbols when the CTS line is

de-asserted. Any symbols in progress of transmission when the CTS line becomes de-asserted will be finished.

RTS auto flow control impacts the receiver only. In fact the name RTS for the control line is incorrect and should be RTR

(Ready to Receive). The receiver will de-assert the RTS (RTR) line when its receive FIFO has a number of empty spaces

left. Normally 3 empty spaces should be enough.

If looping back a mini UART using full auto flow control the logic is fast enough to allow the RTS auto flow level of '10' (De-

assert RTS when the receive FIFO has 1 empty space left).

Auto flow polarity

To offer full flexibility the polarity of the CTS and RTS (RTR) lines can be programmed. This should allow the mini

UART to interface with any existing hardware flow control available.

AUX_MU_STAT_REG Register

Description

The AUX_MU_STAT_REG provides a lot of useful information about the internal status of the mini UART not found on

a normal 16550 UART.

Table 14.

AUX_MU_STAT_REG

Bits Name Description Type Reset

31:28 Reserved. - - -

27:24 Transmit FIFO fill

level

These bits shows how many symbols are stored in the

transmit FIFO

The value is in the range 0-8

RO 0x0

23:20 Reserved. - - -

19:16 Receive FIFO fill

level

These bits shows how many symbols are stored in the

receive FIFO

The value is in the range 0-8

RO 0x0

15:10 Reserved. - - -

9 Transmitter done This bit is set if the transmitter is idle and the transmit FIFO

is empty.

It is a logic AND of bits 3 and 8

RO 0x1

8 Transmit FIFO is

empty

If this bit is set the transmitter FIFO is empty. Thus it can

accept 8 symbols.

RO 0x1

7 CTS line This bit shows the status of the UART1_CTS line. RO 0x0

6 RTS status This bit shows the status of the UART1_RTS line. RO 0x0

5 Transmit FIFO is

full

This is the inverse of bit 1 RO 0x0

BCM2711 ARM Peripherals

2.2. Mini UART 15

Bits Name Description Type Reset

4 Receiver overrun This bit is set if there was a receiver overrun. That is: one or

more characters arrived whilst the receive FIFO was full.

The newly arrived characters have been discarded. This bit

is cleared each time the AUX_MU_LSR_REG register is read.

RO 0x0

3 Transmitter is idle If this bit is set the transmitter is idle.

If this bit is clear the transmitter is busy.

RO 0x1

2 Receiver is idle If this bit is set the receiver is idle.

If this bit is clear the receiver is busy.

This bit can change unless the receiver is disabled

RO 0x1

1 Space available If this bit is set the mini UART transmitter FIFO can accept

at least one more symbol.

If this bit is clear the mini UART transmitter FIFO is full

RO 0x0

0 Symbol available If this bit is set the mini UART receive FIFO contains at

least 1 symbol

If this bit is clear the mini UART receiver FIFO is empty

RO 0x0

Receiver is idle

This bit is only useful if the receiver is disabled. The normal use is to disable the receiver, then check (or wait) until the

bit is set. Now you can be sure that no new symbols will arrive (e.g. now you can change the baudrate…).

Transmitter is idle

This bit tells if the transmitter is idle. Note that the bit will set only for a short time if the transmit FIFO contains data.

Normally you want to use bit 9: Transmitter done.

RTS status

This bit is useful only in receive Auto flow-control mode as it shows the status of the RTS line.

AUX_MU_BAUD_REG Register

Description

The AUX_MU_BAUD_REG register allows direct access to the 16-bit wide baudrate counter.

Table 15.

AUX_MU_BAUD_REG

Bits Name Description Type Reset

31:16 Reserved. - - -

15:0 Baudrate mini UART baudrate counter RW 0x0000

This is the same register as is accessed using the DLAB bit and the first two registers, but much easier to access.

2.3. Universal SPI Master (2x)

The two universal SPI masters are secondary low throughput SPI interfaces. Like the mini UART the devices need to be

enabled before they can be used.

BCM2711 ARM Peripherals

2.3. Universal SPI Master (2x) 16

If the system clock is 250 MHz and the speed field is zero the SPI clock frequency is 125 MHz. The practical SPI clock will

be lower as the I/O pads can not transmit or receive signals at such high speed. The lowest SPI clock frequency with a

250 MHz system clock is 30.5 KHz.

The hardware has an option to add hold time to the MOSI signal against the SPI clk. This is again done using the system

clock. So a 250 MHz system clock will add hold times in units of 4 ns. Hold times of 0, 1, 4 and 7 system clock cycles can

be used. (So at 250MHz an additional hold time of 0, 4, 16 and 28 ns can be achieved). The hold time is additional to the

normal output timing as specified in the data sheet.

2.3.2. Interrupts

The SPI block has two interrupts: TX FIFO is empty, SPI is Idle.

TX FIFO is empty

This interrupt will be asserted as soon as the last entry has been read from the transmit FIFO. At that time the

interface will still be busy shifting out that data. This also implies that the receive FIFO will not yet contain the last

received data. It is possible at that time to fill the TX FIFO again and read the receive FIFO entries which have been

received. There is a RX FIFO level field which tells you exactly how many words are in the receive FIFO. In general at

that time the receive FIFO should contain the number of TX items minus one (the last one still being received). Note

that there is no "receive FIFO full" interrupt as the number of entries received can never be more than the number of

entries transmitted.

SPI is Idle

This interrupt will be asserted when the transmit FIFO is empty and the SPI block has finished all actions (including

the CS-high time). By this time the receive FIFO will have received all data as well.

2.3.3. Long bit streams

The SPI module works in bursts of up to 32 bits. Some SPI devices require data which is longer than 32 bits. To do this

the user must make use of the two different data TX addresses: TX data written to one address causes the CS to remain

asserted. TX data written to the other address causes the CS to be de-asserted at the end of the transmit cycle. So in

order to exchange 96 bits you do the following:

Write the first two data words to one address, then write the third word to the other address.

2.3.4. SPI register details

AUX_SPI1_CNTL0_REG, AUX_SPI2_CNTL0_REG Registers

Description

The AUX_SPIx_CNTL0_REG registers control many features of the SPI interfaces.

Table 16.

AUX_SPI1_CNTL0_REG

AUX_SPI2_CNTL0_REG

Registers

Bits Name Description Type Reset

31:20 Speed Sets the SPI clock speed. spi_clk_freq =

system_clock_freq/2*(speed+1)

RW 0x000

19:17 Chip Selects The pattern output on the CS pins when active. RW 0x7

16 Post-input mode If set the SPI input works in post-input mode.

For details see text further down

RW 0x0

15 Variable CS If 1 the SPI takes the CS pattern and the data from the TX

FIFO

If 0 the SPI takes the CS pattern from bits 17-19 of this

Set this bit only if bit 14 (variable width) is also set

RW 0x0

BCM2711 ARM Peripherals

2.3. Universal SPI Master (2x) 18

Bits Name Description Type Reset

14 Variable width If 1 the SPI takes the shift length and the data from the TX

FIFO

If 0 the SPI takes the shift length from bits 0-5 of this

RW 0x0

13:12 DOUT Hold time Controls the extra DOUT hold time in system clock cycles.

00 : No extra hold time

01 : 1 system clock extra hold time

10 : 4 system clocks extra hold time

11 : 7 system clocks extra hold time

RW 0x0

11 Enable Enables the SPI interface. Whilst disabled the FIFOs can

still be written to or read from

This bit should be 1 during normal operation.

RW 0x0

10 In rising If 1 data is clocked in on the rising edge of the SPI clock

If 0 data is clocked in on the falling edge of the SPI clock

RW 0x0

9 Clear FIFOs If 1 the receive and transmit FIFOs are held in reset (and

thus flushed.)

This bit should be 0 during normal operation.

RW 0x0

8 Out rising If 1 data is clocked out on the rising edge of the SPI clock

If 0 data is clocked out on the falling edge of the SPI clock

RW 0x0

7 Invert SPI CLK If 1 the 'idle' clock line state is high.

If 0 the 'idle' clock line state is low.

RW 0x0

6 Shift out MS bit

first

If 1 the data is shifted out starting with the MS bit. (bit 31 or

bit 23)

If 0 the data is shifted out starting with the LS bit. (bit 0)

RW 0x0

5:0 Shift length Specifies the number of bits to shift

This field is ignored when using 'variable width' mode

RW 0x00

Invert SPI CLK

Changing this bit will immediately change the polarity of the SPI clock output. It is recommended to not do this when

the CS is active, as the connected devices will see this as a clock change.

DOUT hold time

Because the interface runs off fast silicon the MOSI hold time against the clock will be very short. This can cause

considerable problems on SPI slaves. To make it easier for the slave to see the data the hold time of the MOSI out

against the SPI clock out is programmable.

Variable width

In this mode the shift length is taken from the transmit FIFO. The transmit data bits 28:24 are used as shift length and

the data bits 23:0 are the actual transmit data. If the option 'shift MS out first' is selected the first bit shifted out will be

bit 23. The receive data will arrive as normal.

BCM2711 ARM Peripherals

2.3. Universal SPI Master (2x) 19

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BCM2711 ARM 外设手册：2020年版 BCM2835 更新与历史

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