![](https://csdnimg.cn/release/download_crawler_static/18770641/bg13.jpg)
If the system clock is 250 MHz and the speed field is zero the SPI clock frequency is 125 MHz. The practical SPI clock will
be lower as the I/O pads can not transmit or receive signals at such high speed. The lowest SPI clock frequency with a
250 MHz system clock is 30.5 KHz.
The hardware has an option to add hold time to the MOSI signal against the SPI clk. This is again done using the system
clock. So a 250 MHz system clock will add hold times in units of 4 ns. Hold times of 0, 1, 4 and 7 system clock cycles can
be used. (So at 250MHz an additional hold time of 0, 4, 16 and 28 ns can be achieved). The hold time is additional to the
normal output timing as specified in the data sheet.
2.3.2. Interrupts
The SPI block has two interrupts: TX FIFO is empty, SPI is Idle.
TX FIFO is empty
This interrupt will be asserted as soon as the last entry has been read from the transmit FIFO. At that time the
interface will still be busy shifting out that data. This also implies that the receive FIFO will not yet contain the last
received data. It is possible at that time to fill the TX FIFO again and read the receive FIFO entries which have been
received. There is a RX FIFO level field which tells you exactly how many words are in the receive FIFO. In general at
that time the receive FIFO should contain the number of TX items minus one (the last one still being received). Note
that there is no "receive FIFO full" interrupt as the number of entries received can never be more than the number of
entries transmitted.
SPI is Idle
This interrupt will be asserted when the transmit FIFO is empty and the SPI block has finished all actions (including
the CS-high time). By this time the receive FIFO will have received all data as well.
2.3.3. Long bit streams
The SPI module works in bursts of up to 32 bits. Some SPI devices require data which is longer than 32 bits. To do this
the user must make use of the two different data TX addresses: TX data written to one address causes the CS to remain
asserted. TX data written to the other address causes the CS to be de-asserted at the end of the transmit cycle. So in
order to exchange 96 bits you do the following:
Write the first two data words to one address, then write the third word to the other address.
2.3.4. SPI register details
AUX_SPI1_CNTL0_REG, AUX_SPI2_CNTL0_REG Registers
Description
The AUX_SPIx_CNTL0_REG registers control many features of the SPI interfaces.
Table 16.
AUX_SPI1_CNTL0_REG
,
AUX_SPI2_CNTL0_REG
Registers
Bits Name Description Type Reset
31:20 Speed Sets the SPI clock speed. spi_clk_freq =
system_clock_freq/2*(speed+1)
RW 0x000
19:17 Chip Selects The pattern output on the CS pins when active. RW 0x7
16 Post-input mode If set the SPI input works in post-input mode.
For details see text further down
RW 0x0
15 Variable CS If 1 the SPI takes the CS pattern and the data from the TX
FIFO
If 0 the SPI takes the CS pattern from bits 17-19 of this
register
Set this bit only if bit 14 (variable width) is also set
RW 0x0
BCM2711 ARM Peripherals
2.3. Universal SPI Master (2x) 18