SMBus 3.0：系统管理总线协议详解与应用

需积分: 16 125 浏览量更新于2024-07-15 1 收藏 1.05MB PDF 举报

SMBus 3.0 是一种专为系统管理和电源管理任务设计的接口标准，它建立在IIC（Inter-Integrated Circuit）总线的基础上，但提供了更为高效和集中的通信方式。作为一项系统管理总线规范，它旨在简化设备间的数据交换，特别是在处理与电源状态、温度监控、电池管理、硬件配置等系统级任务时。SMBus 3.0 版本发布于2014年12月，由System Management Interface Forum (SMIF) 提供，并强调其提供的是一种无保证的"as is"文档，不承担任何形式的质保，包括但不限于产品适销性、非侵权性或特定用途的适用性。该规范规定了SMBus 的操作细节，包括报文格式、时序要求以及错误检测机制。通过SMBus，系统控制器可以通过两条信号线（数据线和时钟线）来发送和接收信息，这种方式相比于传统的独立控制线，具有更高的效率和更低的复杂性。SMBus 3.0 特别关注兼容性和扩展性，允许设备制造商在不侵犯第三方专利的情况下实现功能集成。值得注意的是，SMBus 不仅仅局限于硬件交互，它还被广泛应用于嵌入式系统、工业自动化、物联网(IoT)等领域，如智能家居设备、服务器电源管理、汽车电子系统等。它的设计目标是提供一种标准化的方法，使得设备能在各种环境下无缝协作，提高整体系统的稳定性和可靠性。在实际应用中，遵循SMBus 3.0 规范的系统设计者必须确保遵循版权和许可条款，避免因侵犯他人知识产权而引发法律纠纷。同时，为了保证系统的正常运行，开发者需要充分理解和掌握该规范中的所有细节，包括数据包解析、错误处理机制和兼容性策略。 SMBus 3.0 是一种关键的IT基础设施组件，对于现代电子设备的低功耗、高效能和智能管理起着至关重要的作用。理解和实施这一标准对于任何涉及系统管理和电源管理的工程师来说都是必不可少的知识。

System Management Bus (SMBus) Specification Version 3.0

Symbol

Meaning

A “don’t care” bit that may have a value of

0 or 1 sent from the slave device to the host

when responding to the Alert Response

Address (ARA)

Figure 1

shows an example of a generic SMBus transaction data structure. Note

the START and STOP conditions are transitions, not bits, and are shown without a

bit count number above the symbol. When shown in a transaction diagram, the

REPEATED START is also a transition, not a bit, and is shown without a bit count

above the symbol.

Figure 1: Generic transaction diagram

3. General Characteristics

SMBus is a two-wire bus. Multiple devices, both bus masters and bus slaves, may be

connected to a SMBus segment. Generally, a bus master device initiates a bus

transfer between it and a single bus slave and provides the clock signals. One

exception to this rule, detailed later, is during initial bus setup when a single master may

initiate transactions with multiple slaves simultaneously. Another exception is during a

ZONE WRITE when a master may be sending data to multiple slaves simultaneously. A

bus slave device can receive data provided by the master or it can provide data to the

master.

Only one device may master the bus at any time. Since more than one device may

attempt to take control of the bus as a master, SMBus provides an arbitration

mechanism that relies on the wired-AND connection of all SMBus device interfaces to

the SMBus.

This specification defines two classes of electrical characteristics, Low Power and

High Power. The first class, originally defined in the SMBus 1.0 and 1.1 specifications,

was designed primarily with Smart Batteries in mind, but could be used with other Low

Power devices. Version 2.0 of the specification introduced an alternative higher power

set of electrical characteristics. This class is appropriate for use when higher drive

capability is required, for example with SMBus devices on PCI add-in cards and for

connecting such cards across the PCI connector between each other and to SMBus

devices on the system board.

This version, Version 3.0, of the SMBus specification introduces operation at higher

bus speeds (400 kHz and 1 MHz) and adds new data protocols for reading or writing

32 bit and 64 bit values. This version also reduces the minimum nominal V

from 3

volts to 1.8 volts.

Devices may be powered by the bus V

or by another power source, V

BUS

, (as with, for

example, Smart Batteries) and will inter-operate as long as they adhere to the SMBus

electrical specifications for their class.

Figure 2

shows an example implementation of a

5 volt SMBus with devices powered by the bus V

inter-operating with self-powered

devices.

Slave Address Wr A Data Byte A P

7 1 1 8

剩余84页未读，继续阅读

笑颜诋毁

粉丝: 1
资源: 3

SMBus 3.0：系统管理总线协议详解与应用

SMBus_3_0_20141220.zip_SMBUS3.0_SMBus协议_smbus_sumbus_sumbus 协议手册

smbus 读取程序

SMBus_3_1_20180319.pdf

PCIExpressCEMSpecificationr3.0-2013.pdf

PCI_Express_CEM_r3.0_008152013.pdf

SMBus 3.0协议手册：SMB总线技术详解

OCP NIC 3.0 SFF Schematic Diagram Example R1v00_20191218a_TN.pdf

GL3523手册.pdf

Fujitsu S7110 S7111.pdf

COM-CFHB6.pdf

最新资源