突破节能极限：EFM32G系列微控制器——高性能与超低功耗的完美结合

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EFM32G系列是Silicon Labs公司推出的一款革命性的微控制器，针对8位至32位市场，特别强调了前所未有的高性能与超低能耗的完美结合。该系列的核心是一款基于ARM Cortex-M3架构的32位处理器，工作频率可达32MHz。这款微控制器在运行模式下的功耗低至180μA/MHz，即使在待机状态下，如使用实时时钟、Brown-out（电源故障）保护以及保持全部RAM和寄存器数据时，也能降低至仅为900nA的极低水平。其特点包括： 1. **能源效率**：作为世界上最为节能的微控制器之一，EFM32G注重在各种工作模式下提供卓越的能效，无论是活跃模式还是睡眠模式，都能显著减少电力消耗。 2. **内存容量**：拥有高达128kB的闪存和16kB的RAM，足以满足大多数应用的需求。 3. **自主和节能外设**：该系列包含一系列自主且高效的外设组件，如定时器、计数器等，能够独立工作并优化系统资源管理。 4. **快速唤醒时间**：仅需2μs的唤醒时间，确保了极短的启动响应时间，有利于实时应用。 5. **集成度高**：集成度高，包括芯片和模拟信号处理能力，提升了整体性能和系统的简化设计。 6. **广泛的应用场景**：EFM32G Gecko系列适用于多种典型应用，如物联网(IoT)设备、电池供电设备、工业自动化和消费电子等领域，特别适合对低功耗有严格要求的项目。 7. **版本更新**：文档提供的是2014年7月的Gecko Family Rev1.30版本，说明Silicon Labs持续关注产品更新和技术支持。 EFM32G系列微控制器以其卓越的性能、低功耗特性和广泛的适用性，在现代电子设计中扮演着关键角色，尤其在追求绿色能源管理和高效能的应用场景中表现出色。开发者在选择微控制器时，如果对低功耗和高性能有严格要求，EFM32G无疑是一个值得考虑的优秀选择。

...the world's most energy friendly microcontrollers

2014-07-02 - Gecko Family - d0001_Rev1.30 16

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Figure 5.2. System Address Space

The embedded SRAM is located at address 0x20000000 in the memory map of the EFM32G. When

running code located in SRAM starting at this address, the Cortex-M3 uses the System bus to fetch

instructions. This results in reduced performance as the Cortex-M3 accesses stack, other data in SRAM

and peripherals using the System bus. To be able to run code from SRAM efficiently, the SRAM is also

mapped in the code space at address 0x10000000. When running code from this space, the Cortex-M3

fetches instructions through the I/D-Code bus interface, leaving the System bus for data access. The

SRAM mapped into the code space can however only be accessed by the CPU, i.e. not the DMA.

5.2.1 Bit-banding

The SRAM bit-band alias and peripheral bit-band alias regions are located at 0x22000000 and

0x42000000 respectively. Read and write operations to these regions are converted into masked single-

bit reads and atomic single-bit writes to the embedded SRAM and peripherals of the EFM32G.

The standard approach to modify a single register or SRAM bit in the aliased regions, requires software

to read the value of the byte, half-word or word containing the bit, modify the bit, and then write the byte,

half-word or word back to the register or SRAM address. Using bit-banding, this read-modify-write can

be done in a single atomic operation. As read-writeback, bit-masking and bit-shift operations are not

necessary in software, code size is reduced and execution speed improved.

The bit-band regions allows addressing each individual bit in the SRAM and peripheral areas of the

memory map. To set or clear a bit in the embedded SRAM, write a 1 or a 0 to the following address:

Memory SRAM Area Set/Clear Bit

...the world's most energy friendly microcontrollers

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5.2.3.2 Access Performance

The Bus Matrix is a multi-layer energy optimized AMBA AHB compliant bus with an internal bandwidth

equal to 4 times a single AHB-bus.

The Bus Matrix accepts new transfers initiated by each master in every clock cycle without inserting

any wait-states. The slaves, however, may insert wait-states depending on their internal throughput and

the clock frequency.

The Cortex-M3, the DMA Controller, and the peripherals run on clocks that can be prescaled separately.

When accessing a peripheral which runs on a frequency equal to or faster than the HFCORECLK, the

number of wait cycles per access, in addition to master arbitration, is given by:

Memory Wait Cycles with Clock Equal or Faster than HFCORECLK

cycles

= 2 + N

slave cycles

, (5.3)

where N

slave cycles

is the wait cycles introduced by the slave.

When accessing a peripheral running on a clock slower than the HFCORECLK, wait-cycles are

introduced to allow the transfer to complete on the peripheral clock. The number of wait cycles per

access, in addition to master arbitration, is given by:

Memory Wait Cycles with Clock Slower than CPU

cycles

= (2 + N

slave cycles

) x f

HFCORECLK

HFPERCLK

, (5.4)

where N

slave cycles

is the number of wait cycles introduced by the slave.

For general register access, N

slave cycles

= 1.

More details on clocks and prescaling can be found in Chapter 11 (p. 95) .

5.3 Access to Low Energy Peripherals (Asynchronous Registers)

5.3.1 Introduction

The Low Energy Peripherals are capable of running when the high frequency oscillator and core system

is powered off, i.e. in energy mode EM2 and in some cases also EM3. This enables the peripherals to

perform tasks while the system energy consumption is minimal.

The Low Energy Peripherals are:

• Liquid Crystal Display driver - LCD

• Low Energy Timer - LETIMER

• Low Energy UART - LEUART

• Pulse Counter - PCNT

• Real Time Counter - RTC

• Watchdog - WDOG

All Low Energy Peripherals are memory mapped, with automatic data synchronization. Because the Low

Energy Peripherals are running on clocks asynchronous to the core clock, there are some constraints

on how register accesses can be done, as described in the following sections.

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