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首页KL25子系列参考手册:ARM Cortex-M0+核心与模块功能
"KL25 Sub-Family Reference Manual.pdf 是一份详细的手册,涵盖了KL25系列微控制器的多个型号,如MKL25Z32VFM4、MKL25Z64VFM4等。该文档的版本号为Rev.3,发布日期为2012年9月,由Freescale Semiconductor, Inc.出版。手册旨在为用户提供关于KL25系列的详细信息,包括其设计目的、适用人群以及一系列技术规范和功能介绍。"
KL25系列是基于ARM Cortex-M0+内核的单片机,属于Freescale半导体的Kinetis L系列。这个系列针对低功耗应用,提供了一系列的嵌入式功能。KL25子家族包含了多种不同内存容量的器件,例如32KB、64KB和128KB闪存的选项。
手册的章节结构清晰,首先介绍了文档的目的和目标读者,以及在文档中使用的符号约定,包括数字系统、排版表示和特殊术语的定义。接着,手册深入讲解了KL25系列的特点,如:
- ARM Cortex-M0+核心模块:这是KL25系列的核心处理器,提供了高效能的计算能力。
- 系统模块:这些模块包括电源管理、复位管理和时钟控制等,对于系统的初始化和运行至关重要。
- 存储器和存储接口:涵盖内部闪存、SRAM以及与外部存储设备的接口,用于存储程序代码和数据。
- 时钟系统:描述了时钟源和时钟分频器,对微控制器的性能和节能有直接影响。
- 安全和完整性模块:可能包括加密硬件和安全特性,以确保数据的安全。
- 模拟模块:如ADC、DAC等,为处理模拟信号提供支持。
- 计时器模块:如PWM、定时器/计数器,用于执行各种定时和计数任务。
- 通信接口:如UART、SPI、I2C等,用于设备间的通信连接。
- 人机接口:可能包括GPIO、LCD控制器等,方便用户交互。
此外,手册还列出了所有可订购的部件编号,方便用户根据实际需求选择合适的器件型号。对于开发人员来说,这份KL25 Sub-Family Reference Manual是理解、设计和开发基于KL25系列微控制器产品的关键参考资料。它详尽地解释了各个模块的功能和配置,有助于工程师进行系统级的设计和故障排查。
Section number Title Page
24.4.3 MCG Internal Reference Clocks..................................................................................................................388
24.4.4 External Reference Clock............................................................................................................................389
24.4.5 MCG Fixed frequency clock .......................................................................................................................389
24.4.6 MCG PLL clock ..........................................................................................................................................390
24.4.7 MCG Auto TRIM (ATM)............................................................................................................................390
24.5 Initialization / Application information........................................................................................................................391
24.5.1 MCG module initialization sequence...........................................................................................................391
24.5.2 Using a 32.768 kHz reference......................................................................................................................393
24.5.3 MCG mode switching..................................................................................................................................394
Chapter 25
Oscillator (OSC)
25.1 Introduction...................................................................................................................................................................405
25.2 Features and Modes......................................................................................................................................................405
25.3 Block Diagram..............................................................................................................................................................406
25.4 OSC Signal Descriptions..............................................................................................................................................406
25.5 External Crystal / Resonator Connections....................................................................................................................407
25.6 External Clock Connections.........................................................................................................................................408
25.7 Memory Map/Register Definitions...............................................................................................................................409
25.7.1 OSC Memory Map/Register Definition.......................................................................................................409
25.8 Functional Description..................................................................................................................................................410
25.8.1 OSC Module States......................................................................................................................................410
25.8.2 OSC Module Modes.....................................................................................................................................412
25.8.3 Counter.........................................................................................................................................................413
25.8.4 Reference Clock Pin Requirements.............................................................................................................413
25.9 Reset..............................................................................................................................................................................414
25.10 Low Power Modes Operation.......................................................................................................................................414
25.11 Interrupts.......................................................................................................................................................................414
KL25 Sub-Family Reference Manual, Rev. 3, September 2012
16 Freescale Semiconductor, Inc.
Section number Title Page
Chapter 26
Flash Memory Controller (FMC)
26.1 Introduction...................................................................................................................................................................415
26.1.1 Overview......................................................................................................................................................415
26.1.2 Features........................................................................................................................................................415
26.2 Modes of operation.......................................................................................................................................................416
26.3 External signal description............................................................................................................................................416
26.4 Memory map and register descriptions.........................................................................................................................416
26.5 Functional description...................................................................................................................................................416
Chapter 27
Flash Memory Module (FTFA)
27.1 Introduction...................................................................................................................................................................419
27.1.1 Features........................................................................................................................................................420
27.1.2 Block Diagram.............................................................................................................................................420
27.1.3 Glossary.......................................................................................................................................................421
27.2 External Signal Description..........................................................................................................................................422
27.3 Memory Map and Registers..........................................................................................................................................422
27.3.1 Flash Configuration Field Description.........................................................................................................422
27.3.2 Program Flash IFR Map...............................................................................................................................423
27.3.3 Register Descriptions...................................................................................................................................424
27.4 Functional Description..................................................................................................................................................432
27.4.1 Flash Protection............................................................................................................................................433
27.4.2 Interrupts......................................................................................................................................................433
27.4.3 Flash Operation in Low-Power Modes........................................................................................................434
27.4.4 Functional Modes of Operation...................................................................................................................434
27.4.5 Flash Reads and Ignored Writes..................................................................................................................434
27.4.6 Read While Write (RWW)...........................................................................................................................435
27.4.7 Flash Program and Erase..............................................................................................................................435
KL25 Sub-Family Reference Manual, Rev. 3, September 2012
Freescale Semiconductor, Inc. 17
Section number Title Page
27.4.8 Flash Command Operations.........................................................................................................................435
27.4.9 Margin Read Commands.............................................................................................................................440
27.4.10 Flash Command Description........................................................................................................................441
27.4.11 Security........................................................................................................................................................454
27.4.12 Reset Sequence............................................................................................................................................456
Chapter 28
Analog-to-Digital Converter (ADC)
28.1 Introduction...................................................................................................................................................................457
28.1.1 Features........................................................................................................................................................457
28.1.2 Block diagram..............................................................................................................................................458
28.2 ADC Signal Descriptions..............................................................................................................................................459
28.2.1 Analog Power (VDDA)...............................................................................................................................460
28.2.2 Analog Ground (VSSA)...............................................................................................................................460
28.2.3 Voltage Reference Select.............................................................................................................................460
28.2.4 Analog Channel Inputs (ADx).....................................................................................................................461
28.2.5 Differential Analog Channel Inputs (DADx)...............................................................................................461
28.3 Register definition.........................................................................................................................................................461
28.3.1 ADC Status and Control Registers 1 (ADCx_SC1n)...................................................................................462
28.3.2 ADC Configuration Register 1 (ADCx_CFG1)...........................................................................................465
28.3.3 ADC Configuration Register 2 (ADCx_CFG2)...........................................................................................467
28.3.4 ADC Data Result Register (ADCx_Rn).......................................................................................................468
28.3.5 Compare Value Registers (ADCx_CVn).....................................................................................................469
28.3.6 Status and Control Register 2 (ADCx_SC2)................................................................................................470
28.3.7 Status and Control Register 3 (ADCx_SC3)................................................................................................472
28.3.8 ADC Offset Correction Register (ADCx_OFS)...........................................................................................474
28.3.9 ADC Plus-Side Gain Register (ADCx_PG).................................................................................................474
28.3.10 ADC Minus-Side Gain Register (ADCx_MG)............................................................................................475
28.3.11 ADC Plus-Side General Calibration Value Register (ADCx_CLPD).........................................................475
28.3.12 ADC Plus-Side General Calibration Value Register (ADCx_CLPS)..........................................................476
KL25 Sub-Family Reference Manual, Rev. 3, September 2012
18 Freescale Semiconductor, Inc.
Section number Title Page
28.3.13 ADC Plus-Side General Calibration Value Register (ADCx_CLP4)..........................................................476
28.3.14 ADC Plus-Side General Calibration Value Register (ADCx_CLP3)..........................................................477
28.3.15 ADC Plus-Side General Calibration Value Register (ADCx_CLP2)..........................................................477
28.3.16 ADC Plus-Side General Calibration Value Register (ADCx_CLP1)..........................................................478
28.3.17 ADC Plus-Side General Calibration Value Register (ADCx_CLP0)..........................................................478
28.3.18 ADC Minus-Side General Calibration Value Register (ADCx_CLMD).....................................................479
28.3.19 ADC Minus-Side General Calibration Value Register (ADCx_CLMS).....................................................479
28.3.20 ADC Minus-Side General Calibration Value Register (ADCx_CLM4).....................................................480
28.3.21 ADC Minus-Side General Calibration Value Register (ADCx_CLM3).....................................................480
28.3.22 ADC Minus-Side General Calibration Value Register (ADCx_CLM2).....................................................481
28.3.23 ADC Minus-Side General Calibration Value Register (ADCx_CLM1).....................................................481
28.3.24 ADC Minus-Side General Calibration Value Register (ADCx_CLM0).....................................................482
28.4 Functional description...................................................................................................................................................482
28.4.1 Clock select and divide control....................................................................................................................483
28.4.2 Voltage reference selection..........................................................................................................................483
28.4.3 Hardware trigger and channel selects..........................................................................................................484
28.4.4 Conversion control.......................................................................................................................................485
28.4.5 Automatic compare function........................................................................................................................493
28.4.6 Calibration function.....................................................................................................................................494
28.4.7 User-defined offset function........................................................................................................................495
28.4.8 Temperature sensor......................................................................................................................................497
28.4.9 MCU wait mode operation...........................................................................................................................497
28.4.10 MCU Normal Stop mode operation.............................................................................................................498
28.4.11 MCU Low-Power Stop mode operation......................................................................................................499
KL25 Sub-Family Reference Manual, Rev. 3, September 2012
Freescale Semiconductor, Inc. 19
Section number Title Page
28.5 Initialization information..............................................................................................................................................499
28.5.1 ADC module initialization example............................................................................................................499
28.6 Application information................................................................................................................................................501
28.6.1 External pins and routing.............................................................................................................................501
28.6.2 Sources of error............................................................................................................................................503
Chapter 29
Comparator (CMP)
29.1 Introduction...................................................................................................................................................................509
29.2 CMP features................................................................................................................................................................509
29.3 6-bit DAC key features.................................................................................................................................................510
29.4 ANMUX key features...................................................................................................................................................511
29.5 CMP, DAC and ANMUX diagram...............................................................................................................................511
29.6 CMP block diagram......................................................................................................................................................512
29.7 Memory map/register definitions..................................................................................................................................514
29.7.1 CMP Control Register 0 (CMPx_CR0).......................................................................................................514
29.7.2 CMP Control Register 1 (CMPx_CR1).......................................................................................................515
29.7.3 CMP Filter Period Register (CMPx_FPR)...................................................................................................517
29.7.4 CMP Status and Control Register (CMPx_SCR).........................................................................................517
29.7.5 DAC Control Register (CMPx_DACCR)....................................................................................................518
29.7.6 MUX Control Register (CMPx_MUXCR)..................................................................................................519
29.8 Functional description...................................................................................................................................................520
29.8.1 CMP functional modes.................................................................................................................................520
29.8.2 Power modes................................................................................................................................................529
29.8.3 Startup and operation...................................................................................................................................530
29.8.4 Low-pass filter.............................................................................................................................................531
29.9 CMP interrupts..............................................................................................................................................................533
29.10 DMA support................................................................................................................................................................533
29.11 CMP Asyncrhonous DMA support...............................................................................................................................534
29.12 Digital-to-analog converter...........................................................................................................................................534
KL25 Sub-Family Reference Manual, Rev. 3, September 2012
20 Freescale Semiconductor, Inc.
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