【免费】TI-SN75LVDS83A.pdf

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SN75LVDS83A

www.ti.com

SLLS980E –JUNE 2009–REVISED NOVEMBER 2016

Product Folder Links: SN75LVDS83A

(1) All typical values are at VCC = 3.3 V, T

= 25°C.

7.5 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP

(1)

MAX UNIT

Input voltage threshold R

= 100 Ω, see Figure 6 VCC/2 V

Differential steady-state output

voltage magnitude

= 100 Ω, see Figure 6 250 450 mV

Δ|V

Change in the steady-state

differential output voltage

magnitude between opposite

binary states

= 100 Ω, see Figure 6 1 35 mV

OC(SS)

Steady-state common-mode

output voltage

R/F

(Dx, CLKin) = 1 ns, see Figure 6 1.125 1.375 V

OC(PP)

Peak-to-peak common-mode

output voltage

R/F

(Dx, CLKin) = 1 ns, see Figure 6 100 mV

High-level input current V

= VCC 25 µA

Low-level input current V

= 0 V ±10 µA

Short-circuit output current

= 0 V ±24 mA

= 0 V ±12 mA

High-impedance state output

current

= 0 V to VCC ±20 µA

pdn

Input pulldown integrated

resistor on all inputs

Dx, CLKSEL, SHTDN, CLKIN 100 kΩ

Quiescent current

SHTDN = V

, disabled, all inputs at

GND

2 100 µA

Supply current (average)

SHTDN = V

, R

= 100 Ω (5 places),

grayscale pattern (Figure 7)

VCC = 3.3 V, f

CLK

= 75 MHz

52.3 62.2 mA

SHTDN = V

, R

= 100 Ω (5 places),

50% transition density pattern (Figure 7),

VCC = 3.3 V, f

CLK

= 75 MHz

53.9 67.1 mA

SHTDN = V

, R

= 100 Ω (5 places),

worst-case pattern (Figure 8),

VCC = 3.6 V, f

CLK

= 75 MHz

65 79.3 mA

SHTDN = V

, R

= 100 Ω (5 places),

worst-case pattern (Figure 8),

CLK

= 100 MHz

96.8 mA

Input capacitance 2 pF

(1) In accordance with the High-K and Low-K thermal metric definitions of EIA/JESD51-2.

(2) This is the inverse of the junction-to-ambient thermal resistance when board-mounted and with no air flow.

7.6 Dissipation Ratings

PACKAGE CIRCUIT BOARD MODEL

(1)

≤ 25°C

DERATING FACTOR

(2)

ABOVE T

= 25°C

= 70°C

POWER RATING

DGG

Low-K 1111 mW 12.3 mW/° C 555 mW

High-K 1730 mW 19 mW/°C 865 mW

SN75LVDS83A

SLLS980E –JUNE 2009–REVISED NOVEMBER 2016

www.ti.com

Product Folder Links: SN75LVDS83A

7.7 Timing Requirements

MIN MAX UNIT

Input clock period 10 100 ns

Input clock modulation (SSC)

with modulation frequency 30 kHz 8%

with modulation frequency 50 kHz 6%

High-level input clock pulse width duration 0.4 × t

0.6 × t

Input signal transition time 3 ns

Data set up time, D0 through D27 before CLKIN (see Figure 5) 2 ns

Data hold time, D0 through D27 after CLKIN 0.8 ns

(1) All typical values are at V

= 3.3 V, T

= 25°C.

(2) |Input clock jitter| is the magnitude of the change in the input clock period.

(3) The output clock cycle-to-cycle jitter is the largest recorded change in the output clock period from one cycle to the next cycle observed

over 15,000 cycles. Tektronix TDSJIT3 Jitter Analysis software was used to derive the maximum and minimum jitter value.

7.8 Switching Characteristics

over operating free-air temperature range (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP

(1)

MAX UNIT

Delay time, CLKOUT↑ after Yn valid

(serial bit position 0, equal D1, D9, D20,

D5)

= 10 ns, |Input clock jitter| < 25 ps

(see Figure 9)

(2)

–0.1 0 0.1 ns

Delay time, CLKOUT↑ after Yn valid

(serial bit position 1, equal D0, D8, D19,

D27)

= 10 ns, |Input clock jitter| < 25 ps

(see Figure 9)

(2)

– 0.1

+ 0.1 ns

Delay time, CLKOUT↑ after Yn valid

(serial bit position 2, equal D7, D18,

D26. D23)

= 10 ns, |Input clock jitter| < 25 ps

(see Figure 9)

(2)

– 0.1

+ 0.1 ns

Delay time, CLKOUT↑ after Yn valid

(serial bit position 3; equal D6, D15,

D25, D17)

= 10 ns, |Input clock jitter| < 25 ps

(see Figure 9)

(2)

– 0.1

+ 0.1 ns

Delay time, CLKOUT↑ after Yn valid

(serial bit position 4, equal D4, D14,

D24, D16)

= 10 ns, |Input clock jitter| < 25 ps

(see Figure 9)

(2)

– 0.1

+ 0.1 ns

Delay time, CLKOUT↑ after Yn valid

(serial bit position 5, equal D3, D13,

D22, D11)

= 10 ns, |Input clock jitter| < 25 ps

(see Figure 9)

(2)

– 0.1

+ 0.1 ns

Delay time, CLKOUT↑ after Yn valid

(serial bit position 6, equal D2, D12,

D21, D10)

= 10 ns,

|Input clock jitter| < 25 ps

(see Figure 9)

(2)

– 0.1

+ 0.1 ns

sk(o)

Output skew, t

Target potential adjustment after

characteristic

–0.1

(–0.15)

0.1

(0.15)

c(o)

Output clock period t

Δt

c(o)

Output clock cycle-to-cycle jitter

(3)

= 10 ns, clean reference clock

(see Figure 10)

±40

= 10 ns with 0.05 UI added noise

modulated at 3 MHz (see Figure 10)

±44

= 10 ns with 0.1 UI added noise

modulated at 3 MHz (see Figure 10)

±42

High-level output clock pulse duration

r/f

Differential output voltage transition time

or t

)

fCLK (see Figure 6) 225 500 ps

Enable time, SHTDN↑ to phase lock

(Yn valid)

CLK

= 100 MHz (see Figure 11) 6 ms

dis

Disable time, SHTDN↓ to off-state

(CLKOUT high-impedance)

CLK

= 100 MHz (see Figure 12) 7 ns

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