Altera FPGA高级综合 cookbook：Verilog实现指南

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"stx_cookbook.pdf - 高级综合烹饪手册：Stratix II、Stratix III和Stratix IV设备设计指南" 这篇文档是Altera公司为FPGA（Field-Programmable Gate Array）设计者提供的一份高级综合烹饪手册，专门针对Stratix系列的FPGA芯片，包括Stratix II、Stratix III和Stratix IV设备。该手册主要关注的是硬件描述语言Verilog的实现，用于图像算法的设计。文档软件版本为9.0，文档版本5.0，发布日期为2009年7月。在FPGA设计中，Verilog是一种广泛使用的硬件描述语言，它允许开发者以结构化的方式描述数字逻辑系统，包括图像处理算法。这份手册可能涵盖了以下关键知识点： 1. **Verilog语法与设计流程**：手册会介绍如何使用Verilog编写和仿真数字电路，包括基本的门级逻辑、组合逻辑和时序逻辑的表示方法，以及模块化设计原则。 2. **FPGA架构理解**：对于Stratix系列，手册可能详细解释了其内部结构，如查找表（LUT）、可编程逻辑块（CLB）、输入/输出单元（IOB）、分布式RAM和嵌入式乘法器等，这些都是实现高效图像算法的基础。 3. **图像处理算法的硬件实现**：手册可能会涵盖如何将各种图像处理算法，如滤波、边缘检测、缩放和旋转等，转换为适合FPGA的硬件描述，这通常涉及到并行计算和流水线优化。 4. **综合策略与优化**：手册可能会讨论如何通过约束设置、逻辑优化和布线技巧来提高设计性能，降低功耗，同时保持设计的面积效率。 5. **时序分析与调试**：文档可能会涉及如何进行时序分析以确保满足设计的时钟速度要求，以及如何利用Altera的开发工具进行问题定位和调试。 6. **知识产权（IP）核的使用**：Stratix系列FPGA支持多种预封装的IP核，可能包括用于图像处理的特定IP，手册可能会讲解如何集成和使用这些IP。 7. **设计验证与仿真**：文档会介绍如何使用Altera的Quartus II等工具进行功能仿真和时序仿真，以验证设计的正确性。 8. **功耗管理和温度控制**：Stratix系列FPGA在高性能运算下可能面临较高的功耗，手册可能会讨论功耗估算和管理策略，以及对工作温度的影响。 9. **硬件调试技术**：手册可能涵盖JTAG接口的使用，以及Altera的增强型边界扫描测试（eBIST）和其他硬件调试工具。 10. **系统级集成**：对于复杂的图像处理系统，如何将FPGA设计与其他处理器（如Cortex-A或PowerPC）和存储器子系统协同工作也是重要的主题。这份"stx_cookbook.pdf"是FPGA开发者，特别是关注图像处理的工程师的一份宝贵资源，它提供了一套详细的设计指南，帮助他们有效地利用Stratix系列FPGA实现高效的Verilog算法。

2–8 Chapter 2: Arithmetic

Bit Population Count

Advanced Synthesis Cookbook © July 2009 Altera Corporation

The structure shown in Figure 2–8 is well known among multiply hardware

designers. Note that the carry path cannot propagate along the width, so delay is

limited to a depth of two. This is efficient on Stratix II devices, although it does not fill

the cells the way a 6:3 compressor does. The example design is left unstructured to

allow flattening for speed, and can absorb input side logic such as multiplier AND

gates.

f The example files are available on the Altera website at the following URL:

www.altera.com/literature/manual/cookbook.zip.

Bit Population Count

An efficient method to count the number of ones or zeros in a binary word is to use

compressors followed by an adder tree. The C-style method of using a “for“ loop with

a shift and conditional +1 tends to create a stick-like structure which is difficult for the

synthesis tools to interpret. In the best case, it requires a significant amount of runtime

for analysis and balancing (see Figure 2–9).

The ideal crossover from compression to propagate addition is width specific. For bit

width of 4 or 5 use propagate adders. For lower bit widths use compressors. The

example thirtysix_six_comp.v shows a 36-input compressor suitable for bit

population counting on 32-bit numbers.

f The example files are available on the Altera website at the following URL:

www.altera.com/literature/manual/cookbook.zip.

Splitting Adder Chains

The Stratix II ALM contains a hard-wired adder chain to speed up the propagation of

the carry signal for arithmetic functions. In some instances, it is desirable to break up a

long chain by exiting the chain for one hop and then resuming, as shown in

Figure 2–10.

Example file arithmetic/wide_compress.v

Figure 2–9. Bit Population Count

Example file arithmetic/thirtysix_six_comp.v

Bit 0

Bit 1

Bit 2

Bit 3

Bit 4

6:3 6:3

…

Further compression

if necessary

Final propagate add

6:3

2–10 Chapter 2: Arithmetic

Adder Trees

Advanced Synthesis Cookbook © July 2009 Altera Corporation

Stratix II ALM implementation requires about three times the area of a simple ripple

carry, and is faster than a standard ripple on long chains. 40 bits is a reasonable

guideline. The exact crossover point depends on the surrounding logic. In a bench

test, a fully registered carry select on a 2S15C3 device ran at 317 MHz using four

blocks of 14-bit ripple. The equivalent 56-bit pure ripple ran at 271 MHz.

The ripple length within a carry select block is a parameter to the example Verilog

HDL. A typical setting for a Stratix II device is 14. This allows the adders to fit within

single LABs with two bits of extra space. The extra positions are used to collect the

carry out signal and to increase the flexibility for placing the carry out multiplexer. A

small speed testing “jig” is included in the select_add_speed_test.v example file.

Some experimentation may be required for the best block width setting at a given

input size.

It is possible to use the SLOAD port to reduce the area cost from triple to double. There

is a parameter in the example file that activates this feature; however, it appears to

negate the speed advantage.

f The example files are available on the Altera website at the following URL:

www.altera.com/literature/manual/cookbook.zip.

Adder Trees

Adder trees are a common building block in digital filters and multipliers. They are

typically implemented with high levels of pipeline. The ALM supports both binary

and ternary adder trees. Roughly speaking, the ternary tree is one-half of the area of a

binary tree, and has one-third fewer levels. Ternary trees are strongly favored in

area-sensitive applications. When favoring speed, the pipelined binary tree is the

more common method. The binary tree has a slightly lower carry delay within each

adder due to lower function complexity. The cost decision can change depending on

routing pressure in the surrounding circuitry and latency requirements.

This example is a parameterized binary adder tree. The input words for summation

are concatenated to form the in_words bus. The parameters NUM_IN_WORDS x

BITS_PER_IN_WORD control the size. The parameter OUT_BITS controls the

expected result size. Some attempt is made to store intermediate results with the

minimum number of bits (for example, 8 bits + 8 bits = 9 bits). The synthesis tools

perform the remaining trimming. The Boolean parameter SIGN_EXT selects sign

Figure 2–12. Carry Select Adders

Example files arithmetic/select_add.v

arithmetic/select_add_speed_test.v

A B A B

A B

Chapter 2: Arithmetic 2–11

Basic Multiplication

versus 0 extension for adding signed numbers. REGISTER_OUTPUT enables pipeline

registers. When the REGISTER_OUTPUT value is 1, a pipeline register is inserted on

the output of every adder node. REGISTER_MIDDLE enables additional registers

embedded in the carry chains. This is intended for high speed applications where the

carry propagation time within a word is too high.

The SHIFT_DIST parameter specifies a shift between input words. This is used for

multiplication. SHIFT_DIST = 0 indicates simple addition of a list of numbers. The

EXTRA_BIT parameter and the I/O signals are used to match the pipeline latency of

an extra signal for convenience in signed multiplication. The lc_mult_signed example

files use this adder in a multiplication context.

f The example files are available on the Altera website at the following URL:

www.altera.com/literature/manual/cookbook.zip.

Basic Multiplication

Stratix II devices use native 36 x 36 multiply-accumulate (MAC) blocks to implement

most multipliers. There is special hardware for packing 18x18 and 9x9 data widths.

The report file lists the number of 9x9 DSP elements used. One 36x36 multiplier uses

all 8 elements in the MAC block. You can access the basic multiplier through the

Verilog HDL/VHDL “*“ operator or through the lpm_mult megafunction. The more

complex output summation and accumulator modes are accessible through the

altmult_add and altmult_accum megafunctions. Direct use of the underlying

MAC_MULT and MAC_OUT WYSIWYG gates can be challenging due to the large

number of ports and parameters with complex legality constraints.

The module mult_32_32 in the example file mult_shift.v implements a

32 x 32=>64-bit multiply with registered inputs and outputs, and individual

signed/unsigned control on the data. It uses a single Stratix II MAC block (eight DSP

elements) implemented with WYSIWYG gates.

f The example files are available on the Altera website at the following URL:

www.altera.com/literature/manual/cookbook.zip.

Multiplication With Rotate and Shift Modes

You can enhance a multiplier with a modest amount of external logic (138 ALUTs) to

implement shift and rotate as well as multiply. Using the Quartus II Analysis

Synthesis speed optimization, the 2^n and OR/MUX logic fits within two levels of

logic, allowing the unit to operate at the speed of the multiplier. This example is based

on the Nios II ALU multiplier (Figure 2–13 on page 2–12).

Example files arithmetic/adder_tree.v

arithmetic/adder_tree_tb.v

arithmetic/adder_tree_layer.v

arithmetic/adder_tree_node.v

Example files arithmetic/mult_shift.v (mult_32_32 module)

arithmetic/mult_shift_tb.v

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