LMK5C33216：JESD204B超低抖动时钟同步器在无线通信中的应用

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"TI-LMK5C33216.pdf是TI公司的一款高性能网络时钟发生器、同步器和抖动衰减器，适用于4G和5G无线通信基础设施，如BBU、AAU、RRU和网络交换机等应用。这款芯片具有超低抖动、多种可编程输出格式和高级参考时钟选择功能。" TI的LMK5C33216是一款基于JESD204B标准设计的超低抖动时钟同步器，特别适合需要高精度时钟信号的无线通信系统。它集成了一系列高级功能，包括3个高性能的数字锁相环(DPLL)和3个模拟锁相环(APLL)，以及16路可编程格式的输出，支持不同频率和标准。 1. **BAWAPLL技术**: LMK5C33216中的APLL3利用了体声波(BAW)谐振器技术，可在491.52MHz时实现40fsRMS的极低抖动，确保了时钟信号的卓越质量。 2. **DPLL和APLL配置**: 3个DPLL每个都配有对应的APLL，APLL基准决定了长期频率精度。DPLL具有可编程的环路带宽，范围从0.01Hz到4kHz，而APLL可以独立运行，甚至可以级联以实现频率转换。 3. **输入与输出**: 支持1Hz至800MHz的差分输入，以及无中断切换功能。输出方面，提供1000MHz的LVPECL/LVDS/HSDS，3000MHz的CML，以及200MHz的LVCMOS等多种格式，满足多样化需求。 4. **基准选择与切换**: 基准选择基于优先级，确保了在基准输入变化时的无缝操作。此外，它还具有相位抑制和/或相位压摆控制，以实现无中断的时钟切换。 5. **电源和接口**: LMK5C33216采用3.3V单电源供电，内置LDO。同时，提供了I2C或3线/4线SPI接口，便于用户进行设备配置。 6. **相位构建与保持**: 设备支持相位构建的保持功能，确保在断电或重启后能保持正确的相位状态。零延迟模式下，通过可编程延迟实现即时输出。 7. **用户可编程性**: 内置的EEPROM允许用户自定义系统启动时的时钟配置，增强了系统的适应性和灵活性。 8. **温度耐受性**: 芯片设计可承受高达105°C的PCB工作温度，适应恶劣环境下的应用。 LMK5C33216是通信基础设施中不可或缺的组件，它通过其高度集成的时钟管理功能，为4G和5G无线网络、基站设备以及网络交换机等应用提供了高精度、高稳定性的时钟信号。

7.5 Electrical Characteristics (continued)

Over Recommended Operating Conditions (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Other Characteristics

PHO-VAR

Input-to-output phase offset

variation over PVT

Zero delay mode, RF clocks only, INx =

122.88 MHz, OUTx = 2949.12 MHz or

2457.6 MHz or 1474.56 MHz or 1228.8

MHz or 737.28 MHz or 614.4 MHz or

153.6 MHz or 122.88 MHz

-200 200 ps

ANA-DEL-ERR

Analog delay error for any step

setting

(9)

VCBO = 2457.6 MHz, PLL3_PRI_DIV =

÷5, OUTx = 491.52 MHz, Analog Delay

step = 32.8 ps

-16 16 ps

DIG-DEL

Digital delay step size on device

clock and SYSREF outputs

SYSREF analog delay off for half cycle

steps and

OUT_x_y_SR_CH_DIV_BYPASS = 1

½ VCO

post

divider

cycle

PSNR

Spur induced by power supply

noise (V

= 50 mVpp)

(5)

(6)

Vcc = 3.3V, HSDS, LVDS, and LVPECL

output

-75 dBc

SPUR

Highest Spur level at 100 Hz to

40 MHz offset

(6)

(7)

OUTx

= 122.88 MHz from VCO3, VCO2

= 5625 MHz, and VCO1 = 5000 MHz

-90 dBc

Highest spur level within12 kHz to

40 MHz band

(6)

(7)

OUTx

= 122.88 MHz, AC-DIFF or LVDS

(all outputs operating with differential

level and no SYSREF)

-75 dBc

PLL Clock Output Performance Characteristics

RJ1

RMS phase jitter of DPLL1/

APLL1 (12 kHz to 20 MHz)

(3)

(7)

XO = 38.88 MHz, APLL1 = 5000 MHz

or 5156.25 MHz, OUTx = 312.5 or

322.265625 MHz, all differential output

types

200 250 fs RMS

RJ2

RMS phase jitter of DPLL2/

APLL2 (12 kHz to 20 MHz)

(3)

(7)

XO = 38.88 MHz, APLL2 = 5898.24

MHz or 5650 MHz, OUTx = 245.76

MHz or 312.5 MHz, all differential

output types

120 180 fs RMS

RJ3

RMS phase jitter of DPLL3/

APLL3 (12 kHz to 20 MHz)

(3)

(7)

XO = 38.88 MHz, APLL3 = 2457.6

MHz, OUTx = 245.76 MHz, all

differential output types

50 80 fs RMS

RJ4

RMS phase jitter of DPLL3/

APLL3 (12 kHz to 20 MHz)

(3)

(7)

XO = 38.88 MHz, APLL3 = 2457.6

MHz, OUTx = 491.52 MHz, all

differential output types

40 70 fs RMS

PN-APLL3

Phase Noise of DPLL3/APLL3 at

800 kHz offset

38.88 MHz XO, VCO3 = 2457.6 MHz,

2457.6 MHz CML output

-147 dBc/Hz

TDC

Output close-in phase noise for

DPLL1 and DPLL2

OFFSET

= 100 Hz)

122.88 MHz AC-DIFF or LVDS, TCXO

= 38.88 MHz, f

TDC

> 20 MHz, DPLL-

BW = 1 kHz

-116 dBc/Hz

Output close-in phase noise for

DPLL3

OFFSET

= 100 Hz)

122.88 MHz AC-DIFF or LVDS, TCXO

= 38.88 MHz, f

TDC

> 20 MHz, DPLL-

BW = 1 kHz

-110 dBc/Hz

BW DPLL bandwidth range

(8)

Programmed bandwidth setting 0.01 4000 Hz

DPLL closed-loop jitter

peaking

(11)

= 25 MHz, f

OUT

= 10 MHz, DPLL BW

= 0.1 Hz or 10 Hz

0.1 dB

TOL

Jitter tolerance

Compliant with G.8262 Options 1 and

2, Jitter modulation = 10 Hz, 25.78125

Gbps

6455 UI p-p

HITLESS

Phase transient during hitless

switch

Valid for a single switchover event

between two clock inputs at the same

frequency 122.88 MHz

-100 100 ps

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7.5 Electrical Characteristics (continued)

Over Recommended Operating Conditions (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

HITLESS

Frequency transient during hitless

switch

Valid for a single switchover event

between two clock inputs at the same

frequency 122.88 MHz

-10 10 ppb

(1) Total device current can be estimated by summing the individual IDD_x and IDDO_x per pin for all blocks enabled in a

given configuration.

(2) An output frequency over the f

OUT

max spec is possible, but the output swing may be less than the V

min spec.

(3) Any output clock except OUT2, OUT3, OUT14, or OUT15.

(4) Output groups are (OUT0 and 1), (OUT2 and 3), (OUT4 to 7), (OUT8 to 13) and (OUT14 and 15).

(5) PSNR is the single-sideband spur level (in dBc) measured when sinusoidal noise with amplitude V

and frequency between 100 kHz

and 1 MHz is injected onto VDD and VDDO_x pins.

(6) DJ

SPUR

(ps pk-pk) = [2 × 10

(dBc/20)

/ (π × f

OUT

) × 1E6], where dBc is the PSNR or SPUR level (in dBc) and f

OUT

is the output frequency

(in MHz).

(7) Excludes output crosstalk and integer-boundary spurs.

(8) DPLL loop bandwidth must be less than 1/100 of TDC frequency and less than 1/10 of APLL loop bandwidth.

(9) Analog delay step size and worst case time error is a function of the input frequency to the SYSREF block and analog delay block

configuration. Maximum analog delay error is half the analog delay step size.

(10) Parameter is specified for PLL outputs divided from either VCO domain.

(11) The TICS Pro software configures the closed-loop jitter peaking for 0.1 dB or less based on the programmed DPLL bandwidth setting.

7.6 Timing Diagrams

SCK

SCS

SDO Read

SDI Write/Read

W/R D0/A0

A13...D1/A1

D7 D1 D0

A14

'21¶7&$5(

图 7-1. SPI Write Timing Diagram

SCK

SCS

SDO

SDI

R A0

A13...A1

D7 D6...D1 D0

A14 '21¶7&$5(

'21¶7&$5(

图 7-2. SPI 4-Wire Read Timing Diagram

LMK5C33216

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8 Parameter Measurement Information

8.1 Differential Voltage Measurement Terminology

The differential voltage of a differential signal can be described by two different definitions, causing confusion

when reading data sheets or communicating with other engineers. This section will address the measurement

and description of a differential signal so that the reader is able to understand and distinguish between the two

different definitions when used.

The first definition used to describe a differential signal is the absolute value of the voltage potential between the

inverting and noninverting signal. The symbol for this first measurement is typically V

or V

depending on if

an input or output voltage is being described.

The second definition used to describe a differential signal is to measure the potential of the noninverting signal

with respect to the inverting signal. The symbol for this second measurement is V

and is a calculated

parameter. Nowhere in the IC does this signal exist with respect to ground, it only exists in reference to its

differential pair. V

can be measured directly by oscilloscopes with floating references, otherwise this value can

be calculated as twice the value of V

as described in the first description.

图 8-1 illustrates the two different definitions side-by-side for inputs and 图 8-2 illustrates the two different

definitions side-by-side for outputs. The V

and V

definitions show V

and V

DC levels that the noninverting

and inverting signals toggle between with respect to ground. V

input and output definitions show that if the

inverting signal is considered the voltage potential reference, the noninverting signal voltage potential is now

increasing and decreasing above and below the noninverting reference. Thus the peak-to-peak voltage of the

differential signal can be measured.

and V

are often defined as volts (V) and V

is often defined as volts peak-to-peak (V

图 8-1. Two Different Definitions for Differential Input Signals

图 8-2. Two Different Definitions for Differential Output Signals

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