NI CompactRIO开发实战指南

CompactRIO

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"NI CompactRIO开发者指南是一份英文文档，详细介绍了使用NILabVIEW进行CompactRIO控制器的控制与监控应用的开发流程和最佳实践。文档涵盖了CompactRIO架构、推荐的LabVIEW架构和开发策略，以及不同编程模式的选择和实时应用程序设计。" 在深入探讨CompactRIO开发者指南之前，先来理解一下CompactRIO系统。CompactRIO是一种模块化、可重配置的嵌入式控制系统，结合了实时处理能力和现场可编程门阵列（FPGA）的硬件，适用于工业自动化、测试与测量等各种应用。 1. **CompactRIO架构** - **LabVIEW实时控制器**：运行LabVIEW实时操作系统，负责执行高级控制算法和系统管理任务。 - **可重配置I/O FPGA**：提供高速、低延迟的数据处理能力，可以定制化I/O处理逻辑。 - **I/O模块**：多种类型的输入输出模块，适应各种传感器和执行器，满足不同应用需求。 2. **系统配置** CompactRIO系统可以根据具体应用灵活配置，包括选择合适的控制器、FPGA及I/O模块，以实现最优性能和功能匹配。 3. **设计CompactRIO软件架构** - **参考架构**：文档提供了几种推荐的软件架构，如单进程和多进程模型，帮助开发者理解如何组织应用程序的不同组件。 - **数据通信**：讨论了系统内不同部分之间如何有效地交换数据，确保实时性和可靠性。 - **典型架构**：展示了一个标准的CompactRIO系统架构，并通过案例（如涡轮测试系统）进一步解释其工作原理。 4. **选择编程模式** - **LabVIEW FPGA**：适合需要高性能、低延迟、定制化I/O操作的场合，例如信号调理和高速数据采集。 - **LabVIEW FPGA接口模式**：在FPGA与实时控制器之间建立通信，用于将实时系统与自定义FPGA逻辑集成。 - **CompactRIO扫描模式**：适用于传统的I/O扫描和设备驱动，适合周期性数据采集和控制。 - **混合模式**：结合FPGA和扫描模式的优点，根据应用需求灵活切换。 5. **设计LabVIEW实时应用** - **顶层RTOS VI**：设计实时系统的主程序，负责协调所有子VI和任务。 - **确定性和非确定性任务**：在实时系统中，理解如何平衡实时性和响应时间是至关重要的，文档将指导开发者如何设计这样的应用程序。这份开发者指南对于那些需要使用NI CompactRIO平台开发控制和监测应用的专业人士来说，是一份宝贵的参考资料。它不仅提供了基础架构信息，还深入到具体的设计策略和编程模式选择，有助于提高应用的性能和可靠性。

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Typical CompactRIO Architecture

Figure 1.3 shows a common architecture that you can use as a starting point for most control and monitoring

applications. The host VI provides an event-based user interface so an operator can interact with the embedded

system. The RTOS executes high-level control and the FPGA executes low-level control.

There are two network communication paths: one path for sending commands from the user interface to the

CompactRIO hardware and a second path for sending tags (current value data) from the CompactRIO hardware to

the user interface for display. To build a scalable application, you should design your system so that it has a single

command parser task that you can use to interpret and redistribute the command as needed. This ensures that

ongoing critical tasks are not disturbed by the arrival of the command and makes it easy to modify the code to

handle additional commands.

Figure 1.3. Common Software Architecture Control and Monitoring Applications

On the RTOS_Main.vi, the communication task and control task are designed as two separate loops. This is generally

a good practice since the network communication could impact the determinism of the control algorithm if the tasks

are executed within a single loop. Also, the modularity makes it easier to simulate parts of the system. For example,

you could easily swap out the actual control loop with a simulated control loop to test the network communication.

Common Variant Architectures

The control and monitoring architecture is a great starting point for most applications, but if you want to design an

embedded data logger, an embedded monitoring system, or a supervisory control and data acquisition (SCADA)

system, you can leverage the more application-specific architectures in the following sections.

Headless Data Logger

A headless CompactRIO system does not require a user interface running on a remote machine. In the case of a

headless data logger, the remote machine might be used for retrieving files that contain logged data from the FTP

server. In this architecture, the FPGA is performing low-level control while acquiring data from NIC Series I/O

modules at a high speed. This data is streamed from the FPGA to the RTOS, where it can be logged to the onboard

memory. The FPGA communication process is separate from the logging engine processes to maximize the rate at

which data is read.



Calculate and display the frequency of the accelerometer data



Monitor temperature to prevent overheating of the turbine during testing



Display the temperature, tachometer velocity (rpm), accelerometer data, and frequency of the accelerometer

data to the UI

To create an architecture for the turbine testing system, start with the control and monitoring architecture shown in

Figure 1.8.

Figure 1.8. Common Software Architecture for Control and Monitoring Applications

This application was implemented in Hybrid Mode, and uses both the RIO Scan Interface and LabVIEW FPGA

Module. LabVIEW FPGA is used for the following tasks:



Turbine Speed Control—This loop generates a PWM signal to control the turbine speed based on the duty

cycle (%) and period (mS) communicated from the LabVIEW Real-Time VI.



Accelerometer and Tachometer Acquisition—This loop takes in the start trigger and acquires data from the

tachometer and accelerometer until it reaches the specified number of samples. It also streams the sensor

data to the LabVIEW Real-Time VI using a DMA first-in-first-out (FIFO) memory buffer.

The RIO Scan Interface is used to monitor the temperature at a rate of 10 Hz

The LabVIEW Real-Time VI has four tasks running in parallel. The data acquisition and analysis task uses a Timed Loop,

and the other three tasks use While Loops. In LabVIEW Real-Time, Timed Loops are used to implement high-priority

tasks, and While Loops are used to implement normal priority tasks. For more information on when to use a Timed Loop

versus a While Loop, see Chapter 3: Designing a LabVIEW Real-Time Application. The following is an overview of

the LabVIEW Real-Time loops:



Data Acquisition and Analysis (High Priority)—This loop communicates with the Accelerometer &

Tachometer Acquisition Loop in the LabVIEW FPGA VI. It sends a trigger to begin the finite acquisition,

retrieves accelerometer data from the DMA FIFO, and sends the collected and analyzed data to the user

interface for display. It also retrieves tachometer data and converts it to revolutions per minute.



Turbine PWM Characteristics—This loop monitors the temperature, and if it rises above the maximum limit,

it shuts down the turbine.



Message Handler—This loop receives any UI commands and distributes them to the appropriate real-time or

FPGA process.

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