MC9S08DZ60 Series Data Sheet, Rev. 1 Draft E
Freescale Semiconductor 17
Subject to Change
Section Number Title Page
Chapter 16
Timer Pulse-Width Modulator (S08TPMV2)
16.1 Introduction ...................................................................................................................................317
16.1.1 Features ...........................................................................................................................319
16.1.2 Block Diagram ................................................................................................................319
16.2 External Signal Description ..........................................................................................................321
16.2.1 External TPM Clock Sources ..........................................................................................321
16.2.2 TPMxCHn — TPMx Channel n I/O Pins .......................................................................321
16.3 Register Definition ........................................................................................................................321
16.3.1 Timer x Status and Control Register (TPMxSC) ............................................................322
16.3.2 Timer x Counter Registers (TPMxCNTH:TPMxCNTL) ................................................323
16.3.3 Timer x Counter Modulo Registers (TPMxMODH:TPMxMODL) ...............................324
16.3.4 Timer x Channel n Status and Control Register (TPMxCnSC) ......................................325
16.3.5 Timer x Channel Value Registers (TPMxCnVH:TPMxCnVL) ......................................326
16.4 Functional Description ..................................................................................................................327
16.4.1 Counter ............................................................................................................................327
16.4.2 Channel Mode Selection .................................................................................................328
16.4.3 Center-Aligned PWM Mode ...........................................................................................330
16.5 TPM Interrupts ..............................................................................................................................331
16.5.1 Clearing Timer Interrupt Flags .......................................................................................331
16.5.2 Timer Overflow Interrupt Description ............................................................................331
16.5.3 Channel Event Interrupt Description ..............................................................................332
16.5.4 PWM End-of-Duty-Cycle Events ...................................................................................332
Chapter 17
Development Support
17.1 Introduction ...................................................................................................................................333
17.1.1 Features ...........................................................................................................................335
17.2 Background Debug Controller (BDC) ..........................................................................................335
17.2.1 BKGD Pin Description ...................................................................................................336
17.2.2 Communication Details ..................................................................................................337
17.2.3 BDC Commands .............................................................................................................341
17.2.4 BDC Hardware Breakpoint .............................................................................................343
17.3 On-Chip Debug System (DBG) ....................................................................................................344
17.3.1 Comparators A and B ......................................................................................................344
17.3.2 Bus Capture Information and FIFO Operation ...............................................................344
17.3.3 Change-of-Flow Information ..........................................................................................345
17.3.4 Tag vs. Force Breakpoints and Triggers .........................................................................345
17.3.5 Trigger Modes .................................................................................................................346
17.3.6 Hardware Breakpoints ....................................................................................................348
17.4 Register Definition ........................................................................................................................348
17.4.1 BDC Registers and Control Bits .....................................................................................348