16
DS90UB962-Q1
ZHCSIP7 –AUGUST 2018
www.ti.com.cn
Copyright © 2018, Texas Instruments Incorporated
CSI-2 Timing Specifications (continued)
Over recommended operating supply and temperature ranges unless otherwise specified.
PARAMETER TEST CONDITIONS
PIN OR
FREQUENCY
MIN TYP MAX UNIT
t
D-TERM-EN
Time for the Data Lane
receiver to enable the HS line
termination
CSI_D0P,
CSI_D0N,
CSI_D1P,
CSI_D1N,
CSI_D2P,
CSI_D2N,
CSI_D3P,
CSI_D3N,
CSI_CLKP,
CSI_CLKN
Time for Dn
to reach V-
TERM-EN
35 +
4×UI
INST
ns
t
EOT
Transmitted time interval from
the start of t
HS-TRAIL
to the
start of the LP-11 state
following a HS burst
105 +
12×UI
INST
ns
t
HS-EXIT
Time that the transmitter
drives LP=11 following a HS
burst
100 ns
t
HS-PREPARE
Data Lane HS Entry
40 +
4×UI
INST
85 +
6×UI
INST
ns
t
HS-PREPARE
+ t
HS-ZERO
t
HS-PREPARE
+ time that the
transmitter drives the HS-0
state prior to transmitting the
Sync sequence
145 +
10×UI
INST
ns
t
HS-SETTLE
Time interval during which the
HS receiver shall ignore any
Data Lane HS transitions,
starting from the beginning of
t
HS-SETTLE
85 +
6×UI
INST
145 +
10×UI
INST
ns
t
HS-SKIP
Time interval during which the
HS-RX should ignore any
transitions on the Data Lane,
following a HS burst. The end
point of the interval is defined
as the beginning of the LP-11
state following the HS burst.
40
55 +
4×UI
INST
ns
t
HS-TRAIL
Data Lane HS Exit
CSI_D0P,
CSI_D0N,
CSI_D1P,
CSI_D1N,
CSI_D2P,
CSI_D2N,
CSI_D3P,
CSI_D3N,
CSI_CLKP,
CSI_CLKN
60 +
4×UI
INST
ns
t
LPX
Transmitted length of LP state 50 ns
t
WAKEUP
Recovery Time from Ultra Low
Power State (ULPS)
1 ms
t
INIT
Initialization period
CSI_D0P,
CSI_D0N,
CSI_D1P,
CSI_D1N,
CSI_D2P,
CSI_D2N,
CSI_D3P,
CSI_D3N,
CSI_CLKP,
CSI_CLKN
100 µs
6.8 Recommended Timing for the Serial Control Bus
Over I
2
C supply and temperature ranges unless otherwise specified.
MIN TYP MAX UNIT
f
SCL
SCL Clock Frequency
Standard-mode >0 100 kHz
Fast-mode >0 400 kHz
Fast-mode Plus >0 1 MHz
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