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首页Intel 100 Series Chipset 家族数据手册:Skylake PCH详析
Intel 100 Series Chipset 家族数据手册:Skylake PCH详析
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更新于2024-07-19
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"Intel 100系列芯片组数据表,主要涵盖了Skylake系列平台控制器中枢(PCH)的信息。"
Intel的100系列芯片组是为支持第六代Skylake微架构的处理器设计的,它在计算平台中扮演着核心角色,负责管理I/O接口、内存控制器以及其他关键功能。此数据手册分为两卷,此处提到的是第二卷,专注于PCH-H的寄存器信息。
平台控制器中枢(PCH)是Intel芯片组的重要组成部分,它连接CPU与各种外围设备,如内存、显卡、USB端口、SATA接口和PCI Express通道。在Skylake平台中,PCH-H是针对高性能桌面平台的变体,提供了更丰富的I/O选项和更高的带宽。
该文档编号为332691-001EN,发布于2015年8月,详细列出了PCH-H的寄存器信息,这些信息对于系统开发者、硬件制造商和软件工程师来说至关重要,因为他们需要理解并配置这些寄存器来实现最佳的系统性能和兼容性。
文档指出,使用该文档进行任何侵权或其他法律分析时,必须获得Intel的非独家、免版税许可。同时强调,文档本身并不授予任何知识产权的许可。这意味着Intel保留对其技术的所有权,并且可能包含设计缺陷或错误(称为errata),这些可能会使产品偏离公布的规格。用户应与Intel代表联系获取最新的产品规格和路线图。
值得注意的是,Intel的技术可能需要启用特定的硬件、软件或服务激活。这通常涉及到BIOS/UEFI设置、驱动程序更新或操作系统支持。用户在购买系统或组件时应咨询系统制造商或零售商以确保兼容性。
所有提供的信息都可能随时更改,而无需提前通知。因此,保持与Intel的最新通讯是确保采用最新技术信息的关键。
Intel 100系列芯片组数据表是开发、调试和优化基于Skylake处理器系统的基础参考材料,涵盖了从基本的硬件连接到高级功能的详细信息。对于那些希望深入理解硬件工作原理或者进行系统优化的专业人士来说,这是一个不可或缺的资源。
16 332691-001EN
5.2.260Input/Output Processing Pipe's Host Connection x Linear DMA Position
Upper (OPPHC13LDPU)—Offset 4ADCh ....................................................397
5.2.261Input/Output Processing Pipe's Host Connection x Linear Link Position
Lower (OPPHC14LLPL)—Offset 4AE0h......................................................398
5.2.262Input/Output Processing Pipe's Host Connection x Linear Link Position
Upper (OPPHC14LLPU)—Offset 4AE4h......................................................398
5.2.263Input/Output Processing Pipe's Host Connection x Linear DMA Position
Lower (OPPHC14LDPL)—Offset 4AE8h .....................................................399
5.2.264Input/Output Processing Pipe's Host Connection x Linear DMA Position
Upper (OPPHC14LDPU)—Offset 4AECh.....................................................399
5.2.265Input/Output Processing Pipe's Link Connection x Control
(IPPLC7CTL)—Offset 4AF0h....................................................................400
5.2.266Input/Output Processing Pipe's Link Connection x Format
(IPPLC7FMT)—Offset 4AF4h ...................................................................401
5.2.267Input/Output Processing Pipe's Link Connection x Linear Link Position
Lower (IPPLC7LLPL)—Offset 4AF8h .........................................................402
5.2.268Input/Output Processing Pipe's Link Connection x Linear Link Position
Upper (IPPLC7LLPU)—Offset 4AFCh.........................................................402
5.2.269Input/Output Processing Pipe's Link Connection x Control
(IPPLC8CTL)—Offset 4B00h....................................................................403
5.2.270Input/Output Processing Pipe's Link Connection x Format
(IPPLC8FMT)—Offset 4B04h ...................................................................404
5.2.271Input/Output Processing Pipe's Link Connection x Linear Link Position
Lower (IPPLC8LLPL)—Offset 4B08h .........................................................405
5.2.272Input/Output Processing Pipe's Link Connection x Linear Link Position
Upper (IPPLC8LLPU)—Offset 4B0Ch.........................................................405
5.2.273Input/Output Processing Pipe's Link Connection x Control
(IPPLC9CTL)—Offset 4B10h....................................................................406
5.2.274Input/Output Processing Pipe's Link Connection x Format
(IPPLC9FMT)—Offset 4B14h ...................................................................407
5.2.275Input/Output Processing Pipe's Link Connection x Linear Link Position
Lower (IPPLC9LLPL)—Offset 4B18h .........................................................408
5.2.276Input/Output Processing Pipe's Link Connection x Linear Link Position
Upper (IPPLC9LLPU)—Offset 4B1Ch.........................................................408
5.2.277Input/Output Processing Pipe's Link Connection x Control
(IPPLC10CTL)—Offset 4B20h..................................................................409
5.2.278Input/Output Processing Pipe's Link Connection x Format
(IPPLC10FMT)—Offset 4B24h .................................................................410
5.2.279Input/Output Processing Pipe's Link Connection x Linear Link Position
Lower (IPPLC10LLPL)—Offset 4B28h........................................................411
5.2.280Input/Output Processing Pipe's Link Connection x Linear Link Position
Upper (IPPLC10LLPU)—Offset 4B2Ch.......................................................411
5.2.281Input/Output Processing Pipe's Link Connection x Control
(IPPLC11CTL)—Offset 4B30h..................................................................412
5.2.282Input/Output Processing Pipe's Link Connection x Format
(IPPLC11FMT)—Offset 4B34h .................................................................413
5.2.283Input/Output Processing Pipe's Link Connection x Linear Link Position
Lower (IPPLC11LLPL)—Offset 4B38h........................................................414
5.2.284Input/Output Processing Pipe's Link Connection x Linear Link Position
Upper (IPPLC11LLPU)—Offset 4B3Ch.......................................................414
5.2.285Input/Output Processing Pipe's Link Connection x Control
(IPPLC12CTL)—Offset 4B40h..................................................................415
5.2.286Input/Output Processing Pipe's Link Connection x Format
(IPPLC12FMT)—Offset 4B44h .................................................................416
5.2.287Input/Output Processing Pipe's Link Connection x Linear Link Position
Lower (IPPLC12LLPL)—Offset 4B48h........................................................417
Datasheet, Volume 2 of 2 17
5.2.288Input/Output Processing Pipe's Link Connection x Linear Link Position
Upper (IPPLC12LLPU)—Offset 4B4Ch ...................................................... 417
5.2.289Input/Output Processing Pipe's Link Connection x Control
(IPPLC13CTL)—Offset 4B50h ................................................................. 418
5.2.290Input/Output Processing Pipe's Link Connection x Format
(IPPLC13FMT)—Offset 4B54h................................................................. 419
5.2.291Input/Output Processing Pipe's Link Connection x Linear Link Position
Lower (IPPLC13LLPL)—Offset 4B58h....................................................... 420
5.2.292Input/Output Processing Pipe's Link Connection x Linear Link Position
Upper (IPPLC13LLPU)—Offset 4B5Ch ...................................................... 420
5.2.293Input/Output Processing Pipe's Link Connection x Control
(IPPLC14CTL)—Offset 4B60h ................................................................. 421
5.2.294Input/Output Processing Pipe's Link Connection x Format
(IPPLC14FMT)—Offset 4B64h................................................................. 422
5.2.295Input/Output Processing Pipe's Link Connection x Linear Link Position
Lower (IPPLC14LLPL)—Offset 4B68h....................................................... 423
5.2.296Input/Output Processing Pipe's Link Connection x Linear Link Position
Upper (IPPLC14LLPU)—Offset 4B6Ch ...................................................... 423
5.2.297Input/Output Processing Pipe's Link Connection x Control
(OPPLC9CTL)—Offset 4B70h .................................................................. 424
5.2.298Input/Output Processing Pipe's Link Connection x Format
(OPPLC9FMT)—Offset 4B74h.................................................................. 425
5.2.299Input/Output Processing Pipe's Link Connection x Linear Link Position
Lower (OPPLC9LLPL)—Offset 4B78h........................................................ 426
5.2.300Input/Output Processing Pipe's Link Connection x Linear Link Position
Upper (OPPLC9LLPU)—Offset 4B7Ch ....................................................... 426
5.2.301Input/Output Processing Pipe's Link Connection x Control
(OPPLC10CTL)—Offset 4B80h ................................................................ 427
5.2.302Input/Output Processing Pipe's Link Connection x Format
(OPPLC10FMT)—Offset 4B84h................................................................ 428
5.2.303Input/Output Processing Pipe's Link Connection x Linear Link Position
Lower (OPPLC10LLPL)—Offset 4B88h...................................................... 429
5.2.304Input/Output Processing Pipe's Link Connection x Linear Link Position
Upper (OPPLC10LLPU)—Offset 4B8Ch ..................................................... 429
5.2.305Input/Output Processing Pipe's Link Connection x Control
(OPPLC11CTL)—Offset 4B90h ................................................................ 430
5.2.306Input/Output Processing Pipe's Link Connection x Format
(OPPLC11FMT)—Offset 4B94h................................................................ 431
5.2.307Input/Output Processing Pipe's Link Connection x Linear Link Position
Lower (OPPLC11LLPL)—Offset 4B98h...................................................... 432
5.2.308Input/Output Processing Pipe's Link Connection x Linear Link Position
Upper (OPPLC11LLPU)—Offset 4B9Ch ..................................................... 432
5.2.309Input/Output Processing Pipe's Link Connection x Control
(OPPLC12CTL)—Offset 4BA0h ................................................................ 433
5.2.310Input/Output Processing Pipe's Link Connection x Format
(OPPLC12FMT)—Offset 4BA4h................................................................ 434
5.2.311Input/Output Processing Pipe's Link Connection x Linear Link Position
Lower (OPPLC12LLPL)—Offset 4BA8h...................................................... 435
5.2.312Input/Output Processing Pipe's Link Connection x Linear Link Position
Upper (OPPLC12LLPU)—Offset 4BACh ..................................................... 435
5.2.313Input/Output Processing Pipe's Link Connection x Control
(OPPLC13CTL)—Offset 4BB0h ................................................................ 436
5.2.314Input/Output Processing Pipe's Link Connection x Format
(OPPLC13FMT)—Offset 4BB4h................................................................ 437
5.2.315Input/Output Processing Pipe's Link Connection x Linear Link Position
Lower (OPPLC13LLPL)—Offset 4BB8h...................................................... 438
18 332691-001EN
5.2.316Input/Output Processing Pipe's Link Connection x Linear Link Position
Upper (OPPLC13LLPU)—Offset 4BBCh......................................................438
5.2.317Input/Output Processing Pipe's Link Connection x Control
(OPPLC14CTL)—Offset 4BC0h.................................................................439
5.2.318Input/Output Processing Pipe's Link Connection x Format
(OPPLC14FMT)—Offset 4BC4h ................................................................440
5.2.319Input/Output Processing Pipe's Link Connection x Linear Link Position
Lower (OPPLC14LLPL)—Offset 4BC8h ......................................................441
5.2.320Input/Output Processing Pipe's Link Connection x Linear Link Position
Upper (OPPLC14LLPU)—Offset 4BCCh......................................................441
5.3 .....................................................................................................................442
6SMBus Interface (D31:F4).....................................................................................443
6.1 SMBus Configuration Registers Summary............................................................443
6.1.1 Vendor ID (VID)—Offset 0h....................................................................443
6.1.2 Device ID (DID)—Offset 2h....................................................................444
6.1.3 Command (CMD)—Offset 4h ..................................................................444
6.1.4 Device Status (DS)—Offset 6h................................................................445
6.1.5 Revision ID (RID)—Offset 8h..................................................................446
6.1.6 Programming Interface (PI)—Offset 9h....................................................446
6.1.7 Sub Class Code (SCC)—Offset Ah............................................................447
6.1.8 Base Class Code (BCC)—Offset Bh ..........................................................447
6.1.9 SMBus Memory Base Address_31_0 (SMBMBAR_31_0)—Offset 10h.............447
6.1.10 SMBus Memory Base Address_63_32 (SMBMBAR_63_32)—Offset 14h .........448
6.1.11 SMB Base Address (SBA)—Offset 20h......................................................448
6.1.12 SVID (SVID)—Offset 2Ch.......................................................................449
6.1.13 SID (SID)—Offset 2Eh...........................................................................449
6.1.14 Interrupt Line (INTLN)—Offset 3Ch .........................................................450
6.1.15 Interrupt Pin (INTPN)—Offset 3Dh...........................................................450
6.1.16 Host Configuration (HCFG)—Offset 40h....................................................451
6.1.17 TCO Base Address (TCOBASE)—Offset 50h...............................................451
6.1.18 TCO Control (TCOCTL)—Offset 54h .........................................................452
6.2 SMBus I/O and Memory Mapped I/O Registers Summary ......................................453
6.2.1 Host Status Register Address (HSTS)—Offset 0h.......................................453
6.2.2 Host Control Register (HCTL)—Offset 2h ..................................................454
6.2.3 Host Command Register (HCMD)—Offset 3h.............................................455
6.2.4 Transmit Slave Address Register (TSA)—Offset 4h ....................................456
6.2.5 Data 0 Register (HD0)—Offset 5h ...........................................................456
6.2.6 Data 1 Register (HD1)—Offset 6h ...........................................................457
6.2.7 Host Block Data (HBD)—Offset 7h...........................................................457
6.2.8 Packet Error Check Data Register (PEC)—Offset 8h ...................................458
6.2.9 Receive Slave Address Register (RSA)—Offset 9h......................................458
6.2.10 Slave Data Register (SD)—Offset Ah .......................................................459
6.2.11 Auxiliary Status (AUXS)—Offset Ch .........................................................459
6.2.12 Auxiliary Control (AUXC)—Offset Dh........................................................460
6.2.13 SMLINK_PIN_CTL Register (SMLC)—Offset Eh...........................................461
6.2.14 SMBUS_PIN_CTL Register (SMBC)—Offset Fh ...........................................461
6.2.15 Slave Status Register (SSTS)—Offset 10h................................................462
6.2.16 Slave Command Register (SCMD)—Offset 11h..........................................463
6.2.17 Notify Device Address Register (NDA)—Offset 14h ....................................463
6.2.18 Notify Data Low Byte Register (NDLB)—Offset 16h....................................464
6.2.19 Notify Data High Byte Register (NDHB)—Offset 17h...................................464
6.3 SMBus PCR Registers Summary.........................................................................465
6.3.1 TCO Configuration (TCOCFG)—Offset 0h..................................................465
6.3.2 General Control (GC)—Offset Ch.............................................................466
6.4 .....................................................................................................................466
Datasheet, Volume 2 of 2 19
7SPI Interface (D31:F5)......................................................................................... 467
7.1 SPI Configuration Registers Summary................................................................ 467
7.1.1 Device ID and Vendor ID (BIOS_SPI_DID_VID)—Offset 0h ........................ 467
7.1.2 Status and Command (BIOS_SPI_STS_CMD)—Offset 4h............................ 467
7.1.3 Revision ID (BIOS_SPI_CC_RID)—Offset 8h............................................. 469
7.1.4 BIST, Header Type, Latency Timer, Cache Line Size
(BIOS_SPI_BIST_HTYPE_LT_CLS)—Offset Ch........................................... 469
7.1.5 SPI BAR0 MMIO (BIOS_SPI_BAR0)—Offset 10h........................................ 470
7.1.6 SPI Unsupported Request Status (BIOS_SPI_UR_STS_CTL)—Offset D0h...... 471
7.1.7 BIOS Decode Enable (BIOS_SPI_BDE)—Offset D8h................................... 471
7.1.8 BIOS Control (BIOS_SPI_BC)—Offset DCh............................................... 472
7.2 SPI Memory Mapped Registers Summary............................................................ 474
7.2.1 SPI BIOS MMIO PRI (BIOS_BFPREG)—Offset 0h ....................................... 475
0.1 Hardware Sequencing Flash Status and Control
(BIOS_HSFSTS_CTL)—Offset 4h............................................................. 476
7.2.2 Flash Address (BIOS_FADDR)—Offset 8h................................................. 478
7.2.3 Discrete Lock Bits (BIOS_DLOCK)—Offset Ch ........................................... 478
7.2.4 Flash Data 0 (BIOS_FDATA0)—Offset 10h................................................ 480
7.2.5 Flash Data 1 (BIOS_FDATA1)—Offset 14h................................................ 480
7.2.6 Flash Data 2 (BIOS_FDATA2)—Offset 18h................................................ 481
7.2.7 Flash Data 3 (BIOS_FDATA3)—Offset 1Ch ............................................... 481
7.2.8 Flash Data 4 (BIOS_FDATA4)—Offset 20h................................................ 481
7.2.9 Flash Data 5 (BIOS_FDATA5)—Offset 24h................................................ 482
7.2.10 Flash Data 6 (BIOS_FDATA6)—Offset 28h................................................ 482
7.2.11 Flash Data 7 (BIOS_FDATA7)—Offset 2Ch ............................................... 483
7.2.12 Flash Data 8 (BIOS_FDATA8)—Offset 30h................................................ 483
7.2.13 Flash Data 9 (BIOS_FDATA9)—Offset 34h................................................ 484
7.2.14 Flash Data 10 (BIOS_FDATA10)—Offset 38h............................................ 484
7.2.15 Flash Data 11 (BIOS_FDATA11)—Offset 3Ch............................................ 484
7.2.16 Flash Data 12 (BIOS_FDATA12)—Offset 40h............................................ 485
7.2.17 Flash Data 13 (BIOS_FDATA13)—Offset 44h............................................ 485
7.2.18 Flash Data 14 (BIOS_FDATA14)—Offset 48h............................................ 486
7.2.19 Flash Data 15 (BIOS_FDATA15)—Offset 4Ch............................................ 486
7.2.20 Flash Region Access Permissions (BIOS_FRACC)—Offset 50h...................... 487
7.2.21 Flash Region 0 (BIOS_FREG0)—Offset 54h .............................................. 487
7.2.22 Flash Region 1 (BIOS_FREG1)—Offset 58h .............................................. 488
7.2.23 Flash Region 2 (BIOS_FREG2)—Offset 5Ch .............................................. 489
7.2.24 Flash Region 3 (BIOS_FREG3)—Offset 60h .............................................. 489
7.2.25 Flash Region 4 (BIOS_FREG4)—Offset 64h .............................................. 490
7.2.26 Flash Region 5 (BIOS_FREG5)—Offset 68h .............................................. 490
7.2.27 Flash Protected Range 0 (BIOS_FPR0)—Offset 84h ................................... 491
7.2.28 Flash Protected Range 1 (BIOS_FPR1)—Offset 88h ................................... 492
7.2.29 Flash Protected Range 2 (BIOS_FPR2)—Offset 8Ch ................................... 493
7.2.30 Flash Protected Range 3 (BIOS_FPR3)—Offset 90h ................................... 494
7.2.31 Flash Protected Range 4 (BIOS_FPR4)—Offset 94h ................................... 495
7.2.32 Global Protected Range 0 (BIOS_GPR0)—Offset 98h ................................. 496
7.2.33 Secondary Flash Region Access Permissions (BIOS_SFRACC)—Offset B0h .... 497
7.2.34 Flash Descriptor Observability Control (BIOS_FDOC)—Offset B4h................ 498
7.2.35 Flash Descriptor Observability Data (BIOS_FDOD)—Offset B8h................... 498
7.2.36 Additional Flash Control (BIOS_AFC)—Offset C0h ..................................... 499
7.2.37 Vendor Specific Component Capabilities for Component 0
(BIOS_SFDP0_VSCC0)—Offset C4h......................................................... 499
7.2.38 Vendor Specific Component Capabilities for Component 1
(BIOS_SFDP1_VSCC1)—Offset C8h......................................................... 501
7.2.39 Parameter Table Index (BIOS_PTINX)—Offset CCh ................................... 503
20 332691-001EN
7.2.40 Parameter Table Data (BIOS_PTDATA)—Offset D0h...................................503
7.2.41 SPI Bus Requester Status (BIOS_SBRS)—Offset D4h.................................504
7.3 BIOS Flash Program Registers Summary.............................................................505
7.3.1 Set Strap Msg Lock (SSML)—Offset F0h...................................................505
7.3.2 Set Strap Msg Control (SSMC)—Offset F4h...............................................505
7.3.3 Set Strap Msg Data (SSMD)—Offset F8h ..................................................506
7.4 .....................................................................................................................507
8Integrated GbE (D31:F6)......................................................................................508
8.1 GbE Configuration Registers Summary................................................................508
8.1.1 GbE Vendor and Device Identification Register (GBE_VID_DID)—Offset 0h...508
8.1.2 PCI Command & Status Register (PCICMD_STS)—Offset 4h........................509
8.1.3 Revision Identification & Class Code Register (RID_CC)—Offset 8h ..............511
8.1.4 Cache Line Size Primary Latency Timer & Header Type Register
(CLS_PLT_HEADTYP)—Offset Ch.............................................................511
8.1.5 Memory Base Address Register A (MBARA)—Offset 10h .............................512
8.1.6 Subsystem Vendor & Subsytem ID (DMI_CONFIG11)—Offset 2Ch ...............512
8.1.7 Expansion ROM Base Address Register (ERBA)—Offset 30h ........................513
8.1.8 Capabilities List Pointer Register (CAPP)—Offset 34h .................................513
8.1.9 Interrupt Information & Maximum Latency/Minimum GrantRegister
(INTR_MLMG)—Offset 3Ch.....................................................................514
8.1.10 LAN Disable Control (LANDISCTRL)—Offset A0h........................................514
8.1.11 Lock LAN Disable (LOCKLANDIS)—Offset A4h...........................................515
8.1.12 System Time Control High Register (LTRCAP)—Offset A8h..........................515
8.1.13 Capabilities List and Power Managment Capabilities Register (CLIST1_PMC)—
Offset C8h...........................................................................................516
8.1.14 PCI Power Management Control Status & Data Register (PMCS_DR)—Offset
CCh ....................................................................................................517
8.1.15 Capabilities List 2 & Message Control Register (CLIST2_MCTL)—Offset D0h ..518
8.1.16 Message Address Low Register (MADDL)—Offset D4h ................................519
8.1.17 Message Address High Register (MADDH)—Offset D8h...............................519
8.1.18 Message Data Register (MDAT)—Offset DCh.............................................520
8.2 GbE Memory Mapped I/O Registers Summary......................................................520
8.2.1 Gigabit Ethernet Capabilities and Status (GBECSR_00)—Offset 0h...............521
8.2.2 Gigabit Ethernet Capabilities and Status (GBECSR_18)—Offset 18h .............521
8.2.3 Gigabit Ethernet Capabilities and Status (GBECSR_20)—Offset 20h .............522
8.2.4 Gigabit Ethernet Capabilities and Status (GBECSR_2C)—Offset 2Ch.............523
8.2.5 Gigabit Ethernet Capabilities and Status (GBECSR_F00)—Offset F00h..........523
8.2.6 Gigabit Ethernet Capabilities and Status F10 (GBECSR_F10)—Offset F10h....524
8.2.7 Gigabit Ethernet Capabilities and Status (GBECSR_5400)—Offset 5400h ......524
8.2.8 Gigabit Ethernet Capabilities and Status (GBECSR_5404)—Offset 5404h ......525
8.2.9 Gigabit Ethernet Capabilities and Status (GBECSR_5800)—Offset 5800h ......525
8.2.10 Gigabit Ethernet Capabilities and Status (GBECSR_5B54)—Offset 5B54h......526
8.3 .....................................................................................................................526
9Intel
®
Trace Hub (Intel
®
TH) .................................................................................527
9.1 Intel Trace Huh Configuration Registers Summary................................................527
9.1.1 Vendor and Device Identification (VID)—Offset 0h.....................................527
9.1.2 Command and Status Register (CMD)—Offset 4h ......................................528
9.1.3 Revision ID (RID)—Offset 8h..................................................................529
9.1.4 Header Type (HT)—Offset Ch .................................................................529
9.1.5 MTB Low BAR (MTB_LBAR)—Offset 10h ...................................................530
9.1.6 MTB Upper BAR (MTB_UBAR)—Offset 14h................................................531
9.1.7 SW Low BAR (SW_LBAR)—Offset 18h......................................................531
9.1.8 SW Upper BAR (SW_UBAR)—Offset 1Ch ..................................................532
9.1.9 RTIT Low BAR (RTIT_LBAR)—Offset 20h ..................................................532
剩余1386页未读,继续阅读
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