TCA6416A：低电压16位I2C/SMBus I/O扩展器

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"TCA6416A是一款低电压16位I2C和SMBus I/O扩展器，具有中断输出、复位功能和配置寄存器。这款芯片适用于需要在不同电压等级之间进行双向电平转换的场合，支持1.8V至5.5V的操作电源电压范围，并且其I/O端口能承受5V的电压。TCA6416A包含一个主动低电平的复位输入(RESET)和一个开漏主动低电平中断输出(INT)，适合于400kHz的快速I2C总线。它还具有输入/输出配置寄存器，允许用户自定义端口极性，并且能够与1.8V、2.5V、3.3V或5V的SCL/SDA通信。" TCA6416A是一款由德州仪器（TI）推出的集成电路，主要用于扩展微控制器的I/O接口。该芯片提供了16个独立的I/O引脚，这些引脚可以通过I2C或SMBus接口进行配置，实现数字输入或输出功能。它的主要特点和功能包括： 1. **宽电压工作范围**：TCA6416A可以在1.65V到5.5V的电源电压下正常工作，这使得它能够适应多种电压环境，包括与不同电压等级的设备进行接口。 2. **5V容限I/O**：所有I/O端口都设计为5V容限，这意味着它们可以承受高达5V的电压，即使在与5V系统交互时也能保持稳定。 3. **复位功能**：TCA6416A集成了一个主动低电平的复位输入(RESET)。当此引脚被拉低时，芯片将复位所有内部状态，恢复到初始配置。 4. **中断输出**：通过一个开漏的中断输出(INT)引脚，TCA6416A可以向主控器发送中断请求，通知有特定的I/O状态变化。 5. **双向电平转换**：TCA6416A支持在不同电压等级（如1.8V、2.5V、3.3V和5V）的系统间进行双向电平转换，这在多电压系统的互连中非常有用。 6. **I2C和SMBus兼容**：该芯片支持400kHz的快速I2C总线协议，也可以与SMBus协议兼容，提供灵活的通信选项。 7. **配置寄存器**：每个I/O端口的极性都可以通过配置寄存器进行反转，允许用户根据需求设置输入或输出的逻辑状态。 8. **封装形式**：TCA6416A提供不同类型的封装，如ZQSPACKAGE、RTWPACKAGE和PWPACKAGE，以适应不同的应用需求。 9. **中心暴露焊盘**：在某些封装中，存在一个中心暴露焊盘，它可以作为次要地线连接，或者保持电气开放。这款芯片在物联网(IoT)设备、智能家居系统、工业自动化以及任何需要扩展微控制器I/O能力的应用中都有广泛的应用。通过I2C接口，主控制器可以轻松地管理和控制这些额外的I/O引脚，实现更复杂的系统功能。

SDA

SCL

S P

StartCondition

StopCondition

SDA

SCL

DataLine

Change

1 2 8 9

NACK

ACK

DataOutput

byTransmitter

DataOutput

byReceiver

SCL From

Master

Start

Condition

ClockPulsefor

Acknowledgment

TCA6416A

SCPS194 – MAY 2009 .......................................................................................................................................................................................................

www.ti.com

A Stop condition, a low-to-high transition on the SDA input/output while the SCL input is high, is sent by the

master (see Figure 1 ).

Any number of data bytes can be transferred from the transmitter to receiver between the Start and the Stop

conditions. Each byte of eight bits is followed by one ACK bit. The transmitter must release the SDA line before

the receiver can send an ACK bit. The device that acknowledges must pull down the SDA line during the ACK

clock pulse, so that the SDA line is stable low during the high pulse of the ACK-related clock period (see

Figure 3 ). When a slave receiver is addressed, it must generate an ACK after each byte is received. Similarly,

the master must generate an ACK after each byte that it receives from the slave transmitter. Setup and hold

times must be met to ensure proper operation.

A master receiver signals an end of data to the slave transmitter by not generating an acknowledge (NACK) after

the last byte has been clocked out of the slave. This is done by the master receiver by holding the SDA line high.

In this event, the transmitter must release the data line to enable the master to generate a Stop condition.

Figure 1. Definition of Start and Stop Conditions

Figure 2. Bit Transfer

Figure 3. Acknowledgment on the I

C Bus

Product Folder Link(s): TCA6416A

Device Address

Slave Address

0 0

R/W

Fixed

Programmable

Control Register and Command Byte

B2 B1

B0B5

TCA6416A

www.ti.com

....................................................................................................................................................................................................... SCPS194 – MAY 2009

Interface Definition

BIT

BYTE

7 (MSB) 6 5 4 3 2 1 0 (LSB)

C slave address L H L L L L ADDR R/ W

P07 P06 P05 P04 P03 P02 P01 P00

I/O data bus

P17 P16 P15 P14 P13 P12 P11 P10

The address of the TCA6416A is shown in Figure 4 .

Figure 4. TCA6416A Address

Address Reference

ADDR I

C BUS SLAVE ADDRESS

L 64 (decimal), 40 (hexadecimal)

H 66 (decimal), 42 (hexadecimal)

The last bit of the slave address defines the operation (read or write) to be performed. A high (1) selects a read

operation, while a low (0) selects a write operation.

Following the successful acknowledgment of the address byte, the bus master sends a command byte, which is

stored in the control register in the TCA6416A. Three bits of this data byte state the operation (read or write) and

the internal registers (input, output, polarity inversion, or configuration) that will be affected. This register can be

written or read through the I

C bus. The command byte is sent only during a write transmission.

Once a new command has been sent, the register that was addressed continues to be accessed by reads until a

new command byte has been sent.

Figure 5. Control Register Bits

Command Byte

CONTROL REGISTER BITS

COMMAND BYTE POWER-UP

(HEX) DEFAULT

B7 B6 B5 B4 B3 B2 B1 B0

0 0 0 0 0 0 0 0 00 Input Port 0 Read byte xxxx xxxx

(1)

0 0 0 0 0 0 0 1 01 Input Port 1 Read byte xxxx xxxx

0 0 0 0 0 0 1 0 02 Output Port 0 Read/write byte 1111 1111

0 0 0 0 0 0 1 1 03 Output Port 1 Read/write byte 1111 1111

0 0 0 0 0 1 0 0 04 Polarity Inversion Port 0 Read/write byte 0000 0000

0 0 0 0 0 1 0 1 05 Polarity Inversion Port 1 Read/write byte 0000 0000

0 0 0 0 0 1 1 0 06 Configuration Port 0 Read/write byte 1111 1111

0 0 0 0 0 1 1 1 07 Configuration Port 1 Read/write byte 1111 1111

(1) Undefined

Product Folder Link(s): TCA6416A

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