基于RTL的VHDL模拟器设计与有效性验证

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本文研究了基于寄存器传输级别（Register Transfer Level, RTL）的VHDL模拟器的设计与验证，即RVS模拟器。该工作主要集中在以下几个关键方面： 1. 实现与设计： RVS模拟器的实现是研究的核心。它以RTL为基础，实现了高效的硬件描述语言工具，使得VHDL设计能够在虚拟平台上进行模拟和调试。VHDL是一种广泛应用于数字电路设计的语言，因其灵活性和可读性而备受青睐。 2. 微程序与逻辑设计：为了测试RVS模拟器的功能，研究者设计了两个CPU架构：微程序SAP-CPU和逻辑SAP-CPU。微程序SAP-CPU采用微程序控制方式，而逻辑SAP-CPU则主要依赖组合逻辑。这些CPU的设计涵盖了控制指令的格式、指令集、寻址方法以及相应的测试程序，以确保它们能正确执行和验证。 3. 指令集和体系结构：指令集是CPU的核心组成部分，定义了处理器如何理解和响应输入的指令。文章详细描述了控制指令的结构和寻址策略，这对于理解和优化CPU性能至关重要。此外，还提供了逻辑SAP-CPU和微程序SAP-CPU的体系结构，展示了设计的细节和组织方式。 4. 验证与评估：实验和分析结果显示，RVS模拟器在处理这两种不同的SAP-CPU设计时表现出良好的性能。它能够准确地模拟CPU的行为，生成满意的仿真结果，证明了其在硬件验证过程中的有效性。这为设计者提供了一个可靠的平台，可以在开发阶段就预测和修正潜在问题。 5. 学术贡献与出版：该研究发表于《能源进展》(Energy Procedia)期刊，由Elsevier BV出版，国际材料科学学会负责选择和同行评审。论文引用了DOI:10.1016/j.egypro.2012.01.084，读者可以通过ScienceDirect获取全文。这一成果对于提高CPU设计的验证效率和准确性具有重要意义，对硬件工程师和研究者来说是一份宝贵的参考资料。这篇研究详细探讨了基于RTL的VHDL模拟器的实现策略，展示了如何用VHDL语言设计和验证微程序和逻辑控制的CPU，以及该模拟器在不同CPU架构上的验证效果，对于深入理解VHDL和硬件模拟技术具有重要的学术价值。

Energy Procedia 16 (2012) 522 – 527

doi:10.1016/j.egypro.2012.01.084

vailable online at www.sciencedirect.com

Energy

Procedia

Energy Procedia 00 (2011) 000–000

www.elsevier.com/locate/procedia

Research on Verification and Implementation of RTL-based

VHDL Simulator

Leng Ming*, Sun Ling-yu

Department of Computer Science, Jinggangshan University, Ji’an 343009, China

Abstract

VHDL simulator based on Register Transfer Level (RTL) is implemented and verified, named RVS. Firstly, we give

the implementation of RVS. Secondly, we design the micro program SAP-CPU and logic SAP-CPU based on VHDL

language, which includes the format of control instruction, instruction set, addressing method, test program and the

architecture of logic SAP-CPU and micro program SAP-CPU. Finally, the experiment and analysis show that the

simulator of RVS perform well and produce encouraging solutions correctly on two SAP-CPU designs controlled by

combinational logic and micro-program.

1. Introduction

The technology of Microelectronic has accelerated the development of modern society. As the core of

computer, microprocessor has been applied in various areas. With the development of microprocessor

technology, traditional methods of logic design couldn’t meet the needs of design and have been replaced

by EDA method step by step. But EDA method is also faced with challenge of high complexity of design.

VHDL and Verilog, as the most representative HDL, which is a formalization language used to describe

the function of hardware circuit, is a powerful and standardized HDL. In the context of increasing need

for LSL design, more and more attention and popularization from the industry make HDL, an

international standard language, the primary HDL in hardware design

[1]

. Essential to HDL design is the

ability to simulate HDL programs. Simulation allows an HDL description of a design to pass design

verification, an important milestone that validates the design's intended function against the code

implementation in the HDL description

[2]

In [3], we design a VHDL simulator based on RTL, which inputs the VLSI design described by VHDL

language of RTL, generates intermediate code by the corresponding compiler, reads the external

excitation signal from the waveform file and applies it on the behavior model. We can decide whether a

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