Xilinx Spartan-6 FPGA DDR3 SDRAM 用户指南关键信息

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本资源是一份Xilinx DDR3 SDRAM的相关用户指南（UG388 v2.3），发布日期为2010年8月9日，针对的是 Spartan-6 FPGA中的Memory Controller模块。这份文档详细介绍了如何在Xilinx硬件设备上开发设计时使用DDR3 SDRAM，旨在帮助工程师理解和实现高速内存接口。首先，DDR3 SDRAM是第四代双倍数据速率同步动态随机访问存储器，它在提高数据传输速度和带宽方面较前一代有所突破。对于Xilinx Spartan-6 FPGA而言，这意味着设计者需要了解如何有效地集成DDR3 SDRAM，并确保满足其严格的时序规范，以充分利用FPGA的性能。用户指南UG388提供了以下关键知识点： 1. **接口与控制**：文档详细说明了如何配置和初始化Memory Controller以与DDR3 SDRAM通信，包括地址、数据和控制信号的正确配置。这包括了解奇偶校验、CAS、RAS、CS等控制信号的作用以及它们在数据传输过程中的协同工作。 2. **时序参数**：DDR3 SDRAM的工作速度依赖于严格的时钟周期、读写延迟和其他时序参数。用户指南会列出这些参数，以确保系统能按照DDR3 SDRAM制造商提供的规格进行操作。 3. **错误检测与纠正**：文档可能涵盖如何处理和避免常见的DDR3 SDRAM错误，如奇偶错误、突发错误等，以及如何启用ECC（错误检查和纠正）功能来提升数据完整性。 4. **电源管理**：DDR3 SDRAM有特定的电源需求，包括VDDQ、VREFN等电压管理。指南会提供如何在FPGA中管理这些电压以保持最佳性能和功耗平衡。 5. **软件支持**：文档可能会提到Xilinx提供的软件工具，如Xilinx ISE或 Vivado，用于DDR3 SDRAM的配置和验证，以及相应的驱动程序和例程。 6. **版权与许可**：使用此文档必须遵循Xilinx的条款，不得擅自复制、分发或修改，除非得到书面许可。Xilinx还强调，文档提供的信息仅供参考，不承担任何关于技术支持或更新的责任。 7. **免责声明**：最后，Xilinx明确表示对文档的使用负有责任，不保证其准确无误，且有权随时更新文档内容，无需通知用户。这份Xilinx DDR3 SDRAM用户指南是FPGA开发者必备的参考资料，它提供了在Spartan-6 FPGA中集成和优化DDR3 SDRAM的全面指导，以便设计出高性能、稳定和兼容的系统。

Spartan-6 FPGA Memory Controller www.xilinx.com 11

UG388 (v2.3) August 9, 2010

Block Diagram

The single data rate (SDR) user interface to the MCB inside the FPGA can be configured for

one to six ports, with each port consisting of a command interface and a read and/or write

data interface. The two 32-bit bidirectional and four 32-bit unidirectional hardware-based

ports inside the MCB can be grouped to create five different port configurations.

Other major components of the MCB include:

•Arbiter

Determines which port currently has priority for accessing the memory device.

• Controller

Primary control block that converts the simple requests made at the user interface into

the necessary instructions and sequences required to communicate with the memory.

• Datapath

Handles the flow of write and read data between the memory device and the user

logic.

• Physical Interface (PHY)

Converts the controller instructions into the actual timing relationships and DDR

signaling necessary to communicate with the memory device.

• Calibration Logic

Calibrates the PHY for optimal performance and reliability.

X-Ref Target - Figure 1-1

Figure 1-1: Spartan-6 FPGA Memory Controller Block (IP Wrapper View)

UG388_c1_01_050409

32-Bit

Bidirectional

Arbiter

PHY

IOB

Datapath

IP Wrapper

Spartan-6 FPGA

Memory

Controller

Calibration

Logic

DDR

DDR2

DDR3

LPDDR

32-Bit

Bidirectional

32-Bit

Unidirectional

32-Bit

Unidirectional

32-Bit

Unidirectional

32-Bit

Unidirectional

CMD FIFO 0

CMD FIFO 1

CMD FIFO 2

CMD FIFO 3

CMD FIFO 4

CMD FIFO 5

User Logic

Dedicated Routing

I/O Clocking Network

12 www.xilinx.com Spartan-6 FPGA Memory Controller

UG388 (v2.3) August 9, 2010

Chapter 1: Memory Controller Block Overview

Performance

The dedicated MCB cores in Spartan-6 devices enable significantly higher performance

levels than equivalent IP solutions implemented in the FPGA logic. Because memory

bandwidth is often the bottleneck in overall system performance, the MCB cores were

specifically engineered for users looking to maximize memory performance in a low-cost,

low-power FPGA device.

Each MCB core supports the memory interface data rates and total memory bandwidth

specifications shown in Table 1-1. Peak bandwidth for a single MCB memory interface is

calculated for the three supported interface widths.

Note:

The MCB supports Standard and Extended performance modes depending on the selected

CCINT

operating conditions. Peak data rates shown in Tabl e 1- 1 represent maximum performance

when using the V

CCINT

range in Extended performance mode. Refer to Table 2 (Recommended

Operating Conditions) and the Performance Characteristics section in DS162, Spartan-6 FPGA Data

Sheet: DC and Switching Characteristics for V

CCINT

operating conditions and performance

specifications for Standard and Extended modes.

Table 1-1: Memory Interface Data Rates and Peak Bandwidth for Each MCB

Memory Type

Data Rate:

Mb/s DDR (MHz Clock)

Peak Bandwidth per MCB Interface (Gb/s)

Minimum Maximum

(1)

4-Bit 8-Bit 16-Bit

DDR 167 Mb/s

(2)

(83.3 MHz)

400 Mb/s

(200 MHz)

1.6Gb/s 3.2Gb/s 6.4Gb/s

DDR2 250 Mb/s

(2)

(125 MHz)

800 Mb/s

(400 MHz)

3.2 Gb/s 6.4 Gb/s 12.8 Gb/s

DDR3 606 Mb/s

(2)

(303 MHz)

800 Mb/s

(400 MHz)

3.2 Gb/s 6.4 Gb/s 12.8 Gb/s

LPDDR 60 Mb/s

(2)

(30 MHz)

400 Mb/s

(200 MHz)

1.6Gb/s 3.2Gb/s 6.4Gb/s

Notes:

1. The maximum MCB data rate shown does not apply to all speed grades. Refer to DS162, Spartan-6

FPGA Data Sheet: DC and Switching Characteristics, for performance by speed grade. The

-3N speed-grade devices do not support the MCB.

2. The minimum frequency requirement of the MCB is dictated by the minimum frequency specification

for the memory standard. See Memory Standards in Appendix A for links to the relevant JEDEC

specifications.

14 www.xilinx.com Spartan-6 FPGA Memory Controller

UG388 (v2.3) August 9, 2010

Chapter 1: Memory Controller Block Overview

Supported Memory Configurations

The Spartan-6 FPGA MCB supports a wide range of common memory types,

configurations, and densities, as shown in Table 1-3.

Software and Tool Support

The Spartan-6 FPGA MCB is supported by standard software and tool flows like other soft

and embedded IP blocks offered by Xilinx. For conventional (i.e., non-embedded) FPGA

designs, the MCB can be integrated into a design using the Memory Interface Generator

(MIG) tool, available in the CORE Generator tool.

The MIG tool is used to generate memory interfaces for all Xilinx FPGAs. It produces the

necessary RTL design files, user constraints files (UCFs), and script files for simulation and

implementation of memory solutions offered by Xilinx. The Getting Started chapter in

UG416

, Spartan-6 FPGA Memory Interface Solutions User Guide, contains detailed

step-by-step instructions on how to use the MIG tool to implement memory interfaces

based on the MCB.

For embedded designs (e.g., MicroBlaze™ processor designs), the IP configurator GUI

found in the Xilinx Platform Studio tool within the EDK environment can be used to

specify the memory interface characteristics. In this flow, the MCB serves as the underlying

hardware implementation of the MPMC IP block, available in the EDK library. In addition

to setting up the controller and memory attributes, the tool generates the necessary soft

bridges to the PLB bus, Xilinx Cache Link (XCL), LocalLink (LL), or other specified

interface for connecting EDK peripherals to the resulting memory controller ports.

Table 1-3: Supported Memory Configurations

Memory Density

Width

(# DQ bits)

Memory Type

LPDDR DDR DDR2 DDR3

128 Mb x16 X X

x8 X

x4 X

256 Mb x16 X X X

x8 X X

x4 X X

512Mbx16XXXX

x8 XXX

x4 XXX

1 Gbx16XXXX

x8 XXX

x4 XXX

2 Gb x16 X X

x8 X X

x4 X X

4 Gb

(1)

x16 X

Notes:

1. The MCB supports single-die, 4 Gb memory components (when available from memory suppliers) but

not dual-die, 4 Gb memory components.

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