嵌入式计算：VLIW架构、编译器与工具的探索

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"《嵌入式计算：一种超长指令字方法在架构、编译器和工具中的应用》是一本深入探讨嵌入式计算领域的专著，特别关注了VLIW（Very Long Instruction Word）技术在该领域的潜力。这本书由在该领域有着开创性经验的作者撰写，具有权威性和深度，被赞誉为与计算机架构和编译器优化的经典著作并列的参考书。" 嵌入式计算是一个不断发展的研究前沿，它涵盖了各种设备和系统，如智能家居、自动驾驶汽车和工业自动化等。这些系统通常对性能、功耗和尺寸有严格要求，因此选择合适的计算平台至关重要。VLIW技术在此背景下显得尤为关键，因为它允许在一个指令周期内执行多个操作，从而提高了处理器效率和能效。这本书深入探讨了VLIW架构的各个方面，包括处理器设计、指令集架构（ISA）、并行处理以及如何通过编译器优化来充分利用VLIW的优势。作者们分享了他们的实践经验，使读者能够理解如何将VLIW技术应用于实际的嵌入式系统设计中。编译器在VLIW系统中扮演着至关重要的角色，因为它们负责将高级语言代码转化为能在VLIW处理器上高效执行的指令序列。书中详细讨论了编译器优化技术，如静态多路复用、指令调度和资源分配，这些都是确保VLIW处理器性能的关键。此外，书中还可能涵盖了与VLIW相关的工具链开发，例如性能分析工具、模拟器和调试器，这些都是开发者进行系统级优化所必需的工具。作者之一Paolo Faraboschi在相关项目TERAFLUX中可能也涉及到了这些内容，这表明书中的理论知识与实际工程实践相结合，有助于读者将理论转化为实际应用。《嵌入式计算：一种超长指令字方法在架构、编译器和工具中的应用》是一本深入且全面的参考资料，对于想要了解和掌握VLIW技术在嵌入式系统中的应用的工程师和研究人员来说，它是不可或缺的读物。这本书不仅提供了技术深度，还包含了作者们的智慧，使得读者能够从中受益匪浅，如同书评所述，它值得在任何计算机科学专业人士的书架上占有一席之地。

xiv Contents

1.4.2 Business Model of Embedded Processors........................... 25

1.4.3 Costs and Product Volume ......................................... 26

1.4.4 Software and the Embedded Software Market ...................... 28

1.4.5 Industry Standards ................................................. 28

1.4.6 Product Life Cycle .................................................. 30

1.4.7 The Transition to SoC Design ...................................... 31

Effects of SoC on the Business Model .............................. 34

Centers of Embedded Design ....................................... 35

1.4.8 The Future of Embedded Systems .................................. 36

Connectivity: Always-on Infrastructure ............................ 36

State: Personal Storage ............................................. 36

Administration ..................................................... 37

Security ............................................................ 37

The Next Generation ............................................... 37

1.5 Further Reading ............................................................. 38

1.6 Exercises .................................................................... 40

CHAPTER 2

An Overview of VLIW and ILP.......................................... 45

2.1 Semantics and Parallelism................................................... 46

2.1.1 Baseline: Sequential Program Semantics ........................... 46

2.1.2 Pipelined Execution, Overlapped Execution, and

Multiple Execution Units........................................... 47

2.1.3 Dependence and Program Rearrangement .......................... 51

2.1.4 ILP and Other Forms of Parallelism ................................ 52

2.2 Design Philosophies ......................................................... 54

2.2.1 An Illustration of Design Philosophies: RISC

Versus CISC ........................................................ 56

2.2.2 First Deﬁnition of VLIW ............................................ 57

2.2.3 A Design Philosophy: VLIW ........................................ 59

VLIW Versus Superscalar .......................................... 59

VLIW Versus DSP .................................................. 62

2.3 Role of the Compiler......................................................... 63

2.3.1 The Phases of a High-Performance Compiler ....................... 63

2.3.2 Compiling for ILP and VLIW ....................................... 65

2.4 VLIW in the Embedded and DSP Domains .................................. 69

2.5 Historical Perspective and Further Reading ................................. 71

2.5.1 ILP Hardware in the 1960s and 1970s .............................. 71

Early Supercomputer Arithmetic Units............................. 71

Attached Signal Processors ......................................... 72

Horizontal Microcode .............................................. 72

2.5.2 The Development of ILP Code Generation in the 1980s ............ 73

Acyclic Microcode Compaction Techniques ....................... 73

Cyclic Techniques: Software Pipelining ............................ 75

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Contents xv

2.5.3 VLIW Development in the 1980s ................................... 76

2.5.4 ILP in the 1990s and 2000s ......................................... 77

2.6 Exercises .................................................................... 78

CHAPTER 3

An Overview of ISA Design .............................................. 83

3.1 Overview: What to Hide ..................................................... 84

3.1.1 Architectural State: Memory and Registers ......................... 84

3.1.2 Pipelining and Operational Latency ................................ 85

3.1.3 Multiple Issue and Hazards ........................................ 86

Exposing Dependence and Independence .......................... 86

Structural Hazards.................................................. 87

Resource Hazards................................................... 89

3.1.4 Exception and Interrupt Handling.................................. 89

3.1.5 Discussion.......................................................... 90

3.2 Basic VLIW Design Principles ............................................... 91

3.2.1 Implications for Compilers and Implementations .................. 92

3.2.2 Execution Model Subtleties ........................................ 93

3.3 Designing a VLIW ISA for Embedded Systems .............................. 95

3.3.1 Application Domain................................................ 96

3.3.2 ILP Style............................................................ 98

3.3.3 Hardware/Software Tradeoffs ...................................... 100

3.4

Instruction-set Encoding..................................................... 101

3.4.1 A Larger Deﬁnition of Architecture................................. 101

3.4.2 Encoding and Architectural Style .................................. 105

RISC Encodings .................................................... 107

CISC Encodings .................................................... 108

VLIW Encodings.................................................... 109

Why Not Superscalar Encodings? .................................. 109

DSP Encodings ..................................................... 110

Vector Encodings ................................................... 111

3.5 VLIW Encoding.............................................................. 112

3.5.1 Operation Encoding ................................................ 113

3.5.2 Instruction Encoding ............................................... 113

Fixed-overhead Encoding .......................................... 115

Distributed Encoding ............................................... 115

Template-based Encoding .......................................... 116

3.5.3 Dispatching and Opcode Subspaces ................................ 117

3.6 Encoding and Instruction-set Extensions .................................... 119

3.7 Further Reading ............................................................. 121

3.8 Exercises .................................................................... 121

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xvi Contents

CHAPTER 4

Architectural Structures in ISA Design............................... 125

4.1 The Datapath ................................................................ 127

4.1.1 Location of Operands and Results .................................. 127

4.1.2 Datapath Width..................................................... 127

4.1.3 Operation Repertoire ............................................... 129

Simple Integer and Compare Operations ........................... 131

Carry, Overﬂow, and Other Flags................................... 131

Common Bitwise Utilities .......................................... 132

Integer Multiplication .............................................. 132

Fixed-point Multiplication ......................................... 133

Integer Division .................................................... 135

Floating-point Operations .......................................... 136

Saturated Arithmetic ............................................... 137

4.1.4 Micro-SIMD Operations ............................................ 139

Alignment Issues ................................................... 141

Precision Issues .................................................... 141

Dealing with Control Flow ......................................... 142

Pack, Unpack, and Mix ............................................. 143

Reductions ......................................................... 143

4.1.5 Constants ........................................................... 144

4.2 Registers and Clusters ....................................................... 144

4.2.1 Clustering .......................................................... 145

Architecturally Invisible Clustering ................................ 147

Architecturally Visible Clustering .................................. 147

4.2.2 Heterogeneous Register Files ....................................... 149

4.2.3 Address and Data Registers......................................... 149

4.2.4 Special Register File Features ...................................... 150

Indexed Register Files .............................................. 150

Rotating Register Files.............................................. 151

4.3 Memory Architecture........................................................ 151

4.3.1 Addressing Modes.................................................. 152

4.3.2 Access Sizes ........................................................ 153

4.3.3 Alignment Issues ................................................... 153

4.3.4 Caches and Local Memories ........................................ 154

Prefetching ......................................................... 154

Local Memories and Lockable Caches .............................. 156

4.3.5 Exotic Addressing Modes for Embedded Processing ............... 156

4.4

Branch Architecture ......................................................... 156

4.4.1 Unbundling Branches .............................................. 158

Two-step Branching ................................................ 159

Three-step Branching............................................... 159

4.4.2 Multiway Branches ................................................. 160

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Contents xvii

4.4.3 Multicluster Branches .............................................. 161

4.4.4 Branches and Loops ................................................ 162

4.5 Speculation and Predication................................................. 163

4.5.1 Speculation......................................................... 163

Control Speculation ................................................ 164

Data Speculation ................................................... 167

4.5.2 Predication ......................................................... 168

Full Predication .................................................... 169

Partial Predication.................................................. 170

Cost and Beneﬁts of Predication.................................... 171

Predication in the Embedded Domain .............................. 172

4.6 System Operations .......................................................... 173

4.7 Further Reading ............................................................. 174

4.8

Exercises .................................................................... 175

CHAPTER 5

Microarchitecture Design ................................................. 179

5.1 Register File Design ......................................................... 182

5.1.1 Register File Structure.............................................. 182

5.1.2 Register Files, Technology, and Clustering ......................... 183

5.1.3 Separate Address and Data Register Files .......................... 184

5.1.4 Special Registers and Register File Features ........................ 186

5.2 Pipeline Design.............................................................. 186

5.2.1 Balancing a Pipeline................................................ 187

5.3

VLIW Fetch, Sequencing, and Decoding..................................... 191

5.3.1 Instruction Fetch ................................................... 191

5.3.2 Alignment and Instruction Length ................................. 192

5.3.3 Decoding and Dispersal ............................................ 194

5.3.4 Decoding and ISA Extensions ...................................... 195

5.4 The Datapath ................................................................ 195

5.4.1 Execution Units .................................................... 197

5.4.2 Bypassing and Forwarding Logic ................................... 200

5.4.3 Exposing Latencies ................................................. 202

5.4.4 Predication and Selects............................................. 204

5.5

Memory Architecture........................................................ 206

5.5.1 Local Memory and Caches.......................................... 206

5.5.2 Byte Manipulation.................................................. 209

5.5.3 Addressing, Protection, and Virtual Memory ....................... 210

5.5.4 Memories in Multiprocessor Systems .............................. 211

5.5.5 Memory Speculation ............................................... 213

5.6 The Control Unit ............................................................ 214

5.6.1 Branch Architecture ................................................ 214

5.6.2 Predication and Selects............................................. 215

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xviii Contents

5.6.3 Interrupts and Exceptions .......................................... 216

5.6.4 Exceptions and Pipelining.......................................... 218

Drain and Flush Pipeline Models................................... 218

Early Commit....................................................... 219

Delayed Commit.................................................... 220

5.7 Control Registers ............................................................ 221

5.8 Power Considerations ....................................................... 221

5.8.1 Energy Efﬁciency and ILP .......................................... 222

System-level Power Considerations ................................ 224

5.9 Further Reading ............................................................. 225

5.10

Exercises .................................................................... 227

CHAPTER 6

System Design and Simulation.......................................... 231

6.1 System-on-a-Chip (SoC) ..................................................... 231

6.1.1 IP Blocks and Design Reuse ........................................ 232

A Concrete SoC Example ........................................... 233

Virtual Components and the VSIA Alliance ........................ 235

6.1.2 Design Flows ....................................................... 236

Creation Flow ...................................................... 236

Veriﬁcation Flow ................................................... 238

6.1.3 SoC Buses .......................................................... 239

Data Widths ........................................................ 240

Masters, Slaves, and Arbiters ....................................... 241

Bus Transactions ................................................... 242

Test Modes ......................................................... 244

6.2 Processor Cores and SoC .................................................... 245

6.2.1 Nonprogrammable Accelerators .................................... 246

Reconﬁgurable Logic ............................................... 248

6.2.2 Multiprocessing on a Chip ......................................... 250

Symmetric Multiprocessing ........................................ 250

Heterogeneous Multiprocessing .................................... 251

Example: A Multicore Platform for Mobile Multimedia ............ 252

6.3 Overview of Simulation ..................................................... 254

6.3.1 Using Simulators ................................................... 256

6.4 Simulating a VLIW Architecture ............................................ 257

6.4.1 Interpretation....................................................... 258

6.4.2 Compiled Simulation............................................... 259

Memory ............................................................ 262

Registers............................................................ 263

Control Flow ....................................................... 263

Exceptions.......................................................... 266

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