VHDL实现DES加解密硬件模块

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

package des_lib is
    component des
    port (clk :in std_logic;
          reset :in std_logic;

          encrypt :in std_logic;
          key_in :in std_logic_vector (55 downto 0);
          din :in std_logic_vector (63 downto 0);
          din_valid :in std_logic;
          
          busy :buffer std_logic;
          dout :out std_logic_vector (63 downto 0);
          dout_valid :out std_logic
         );
  end component;
          

  component des_round
    port (clk :in std_logic;
          reset :in std_logic;
          stall :in std_logic;

  encrypt_in :in std_logic;
          encrypt_shift :in std_logic_vector (4 downto 0);
          decrypt_shift :in std_logic_vector (4 downto 0);

          key_in :in std_logic_vector (55 downto 0);
          din :in std_logic_vector (63 downto 0);
          din_valid     :in std_logic;


  encrypt_out :out std_logic;
          key_out :out std_logic_vector (55 downto 0);
          dout :out std_logic_vector (63 downto 0);
          dout_valid :out std_logic
         );
  end component;


  -- Inital permutation
  function des_ip(din :std_logic_vector(63 downto 0))
                  return std_logic_vector;

  -- Final permutation
  function des_fp(din :std_logic_vector(63 downto 0))
                  return std_logic_vector;

  -- Key permutation, converts a 64 bit key into a 56 bit key, ignoring parity
  function des_kp(din   :std_logic_vector (63 downto 0))
                  return std_logic_vector;

  -- Compression Permutation, converts a 56 bit key into a 48 bits.
  function des_cp(din   :std_logic_vector (55 downto 0))
                  return std_logic_vector;

  -- Expansion permutation