PIC16F877微控制器数据手册

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"PIC16F877是Microchip Technology Inc.生产的一款8位CMOS闪存微控制器的数据手册。该手册涵盖了芯片的详细规格、功能、应用和接口信息。" 《PIC16F877数据手册》是开发者和工程师们理解、设计和使用PIC16F877微控制器的重要参考资料。该手册详细介绍了这款微控制器的各项特性，包括： 1. **架构与内部结构**：PIC16F877采用哈佛架构，拥有独立的程序和数据存储空间，这使得它可以同时处理指令和数据，提高执行效率。它有28或40个引脚，8位的CPU，并且集成了闪存存储器用于程序代码。 2. **闪存编程**：微控制器内部的闪存允许用户通过编程接口进行多次擦除和写入操作，方便进行现场程序更新和调试。 3. **寄存器配置**：手册详细列出了所有的控制和状态寄存器，这些寄存器用于配置和监控微控制器的工作状态，如中断设置、定时器控制、波特率生成等。 4. **模拟特性**：PIC16F877具有内置的模拟电路，如比较器、模拟多路复用器和振荡器，支持模拟信号的处理。 5. **数字输入输出**：具备多个可配置的I/O端口，可以作为数字输入或输出，用于连接各种外部设备。 6. **定时器和计数器**：包括定时器和计数器模块，如Timer0、Timer1和Counter，可以实现定时任务和脉冲计数。 7. **中断系统**：支持多种中断源，允许对突发事件进行快速响应。 8. **串行通信**：集成USART（通用同步/异步收发传输器）模块，支持UART、SPI和I²C等串行通信协议。 9. **电源管理**：具有低功耗模式，如空闲模式和掉电模式，便于在电池供电的应用中节省能源。 10. **安全特性**：可能包含防止非法访问和拷贝代码的保护机制。请注意，Microchip Technology Inc.在手册中明确指出，尽管提供了应用建议，但信息可能会有更新，用户应确保使用最新版本的手册。此外，Microchip不对因使用该信息可能引发的专利侵权或其他知识产权纠纷承担责任。除非获得Microchip的书面批准，否则不建议将Microchip的产品用于生命维持系统的关键组件，以避免潜在风险。《PIC16F877数据手册》是工程师开发基于PIC16F877的嵌入式系统时不可或缺的工具，它提供了全面的技术细节和应用指导。

PIC16F87X

DS30292C-page 14  2001 Microchip Technology Inc.

FIGURE 2-4: PIC16F874/873 REGISTER FILE MAP

Indirect addr.

(*)

TMR0

PCL

STATUS

FSR

PORTA

PORTB

PORTC

PCLATH

INTCON

PIR1

TMR1L

TMR1H

T1CON

TMR2

T2CON

SSPBUF

SSPCON

CCPR1L

CCPR1H

CCP1CON

OPTION_REG

PCL

STATUS

FSR

TRISA

TRISB

TRISC

PCLATH

INTCON

PIE1

PCON

PR2

SSPADD

SSPSTAT

00h

01h

02h

03h

04h

05h

06h

07h

08h

09h

0Ah

0Bh

0Ch

0Dh

0Eh

0Fh

10h

11h

12h

13h

14h

15h

16h

17h

18h

19h

1Ah

1Bh

1Ch

1Dh

1Eh

1Fh

80h

81h

82h

83h

84h

85h

86h

87h

88h

89h

8Ah

8Bh

8Ch

8Dh

8Eh

8Fh

90h

91h

92h

93h

94h

95h

96h

97h

98h

99h

9Ah

9Bh

9Ch

9Dh

9Eh

9Fh

20h

A0h

7Fh

FFh

Bank 0

Bank 1

Indirect addr.

(*)

Indirect addr.

(*)

PCL

STATUS

FSR

PCLATH

INTCON

PCL

STATUS

FSR

PCLATH

INTCON

100h

101h

102h

103h

104h

105h

106h

107h

108h

109h

10Ah

10Bh

180h

181h

182h

183h

184h

185h

186h

187h

188h

189h

18Ah

18Bh

17Fh

1FFh

Bank 2

Bank 3

Indirect addr.

(*)

PORTD

(1)

PORTE

(1)

TRISD

(1)

ADRESL

TRISE

(1)

TMR0

OPTION_REG

PIR2

PIE2

RCSTA

TXREG

RCREG

CCPR2L

CCPR2H

CCP2CON

ADRESH

ADCON0

TXSTA

SPBRG

ADCON1

General

Purpose

General

Purpose

1EFh

1F0h

accesses

A0h - FFh

16Fh

170h

accesses

20h-7Fh

TRISB

PORTB

96 Bytes

SSPCON2

10Ch

10Dh

10Eh

10Fh

110h

18Ch

18Dh

18Eh

18Fh

190h

EEDATA

EEADR

EECON1

EECON2

EEDATH

EEADRH

Reserved

(2)

Reserved

(2)

Unimplemented data memory locations, read as ’0’.

* Not a physical register.

Note 1: These registers are not implemented on the PIC16F873.

2: These registers are reserved, maintain these registers clear.

120h

1A0h

File

Address

File

Address

File

Address

File

Address

 2001 Microchip Technology Inc. DS30292C-page 15

PIC16F87X

2.2.2 SPECIAL FUNCTION REGISTERS

The Special Function Registers are registers used by

the CPU and peripheral modules for controlling the

desired operation of the device. These registers are

implemented as static RAM. A list of these registers is

given in Table 2-1.

The Special Function Registers can be classified into

two sets: core (CPU) and peripheral. Those registers

associated with the core functions are described in

detail in this section. Those related to the operation of

the peripheral features are described in detail in the

peripheral features section.

TABLE 2-1: SPECIAL FUNCTION REGISTER SUMMARY

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Value on:

POR,

BOR

Details

page:

Bank 0

00h

(3)

INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 27

01h TMR0 Timer0 Module Register

xxxx xxxx 47

02h

(3)

PCL Program Counter (PC) Least Significant Byte 0000 0000 26

03h

(3)

STATUS IRP RP1 RP0 TO PD ZDCC0001 1xxx 18

04h

(3)

FSR Indirect Data Memory Address Pointer xxxx xxxx 27

05h PORTA

— — PORTA Data Latch when written: PORTA pins when read --0x 0000 29

06h PORTB PORTB Data Latch when written: PORTB pins when read

xxxx xxxx 31

07h PORTC PORTC Data Latch when written: PORTC pins when read

xxxx xxxx 33

08h

(4)

PORTD PORTD Data Latch when written: PORTD pins when read xxxx xxxx 35

09h

(4)

PORTE — — — — — RE2 RE1 RE0 ---- -xxx 36

0Ah

(1,3)

PCLATH — — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 26

0Bh

(3)

INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 20

0Ch PIR1 PSPIF

(3)

ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 22

0Dh PIR2

— (5) — EEIF BCLIF — — CCP2IF -r-0 0--0 24

0Eh TMR1L Holding register for the Least Significant Byte of the 16-bit TMR1 Register

xxxx xxxx 52

0Fh TMR1H Holding register for the Most Significant Byte of the 16-bit TMR1 Register

xxxx xxxx 52

10h T1CON

— — T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 51

11h TMR2 Timer2 Module Register

0000 0000 55

12h T2CON

— TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 55

13h SSPBUF Synchronous Serial Port Receive Buffer/Transmit Register

xxxx xxxx 70, 73

14h SSPCON WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0

0000 0000 67

15h CCPR1L Capture/Compare/PWM Register1 (LSB)

xxxx xxxx 57

16h CCPR1H Capture/Compare/PWM Register1 (MSB)

xxxx xxxx 57

17h CCP1CON

— — CCP1X CCP1Y CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 58

18h RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D

0000 000x 96

19h TXREG USART Transmit Data Register

0000 0000 99

1Ah RCREG USART Receive Data Register

0000 0000 101

1Bh CCPR2L Capture/Compare/PWM Register2 (LSB)

xxxx xxxx 57

1Ch CCPR2H Capture/Compare/PWM Register2 (MSB)

xxxx xxxx 57

1Dh CCP2CON

— — CCP2X CCP2Y CCP2M3 CCP2M2 CCP2M1 CCP2M0 --00 0000 58

1Eh ADRESH A/D Result Register High Byte

xxxx xxxx 116

1Fh ADCON0 ADCS1 ADCS0 CHS2 CHS1 CHS0 GO/DONE

— ADON 0000 00-0 111

Legend:

x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as '0', r = reserved.

Shaded locations are unimplemented, read as ‘0’.

Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose

contents are transferred to the upper byte of the program counter.

2: Bits PSPIE and PSPIF are reserved on PIC16F873/876 devices; always maintain these bits clear.

3: These registers can be addressed from any bank.

4: PORTD, PORTE, TRISD, and TRISE are not physically implemented on PIC16F873/876 devices; read as ‘0’.

5: PIR2<6> and PIE2<6> are reserved on these devices; always maintain these bits clear.

PIC16F87X

DS30292C-page 16  2001 Microchip Technology Inc.

Bank 1

80h

(3)

INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 27

81h OPTION_REG RBPU

INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 19

82h

(3)

PCL Program Counter (PC) Least Significant Byte 0000 0000 26

83h

(3)

STATUS IRP RP1 RP0 TO PD ZDCC0001 1xxx 18

84h

(3)

FSR Indirect Data Memory Address Pointer xxxx xxxx 27

85h TRISA

— — PORTA Data Direction Register --11 1111 29

86h TRISB PORTB Data Direction Register

1111 1111 31

87h TRISC PORTC Data Direction Register

1111 1111 33

88h

(4)

TRISD PORTD Data Direction Register 1111 1111 35

89h

(4)

TRISE IBF OBF IBOV PSPMODE — PORTE Data Direction Bits 0000 -111 37

8Ah

(1,3)

PCLATH — — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 26

8Bh

(3)

INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 20

8Ch PIE1 PSPIE

(2)

ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 21

8Dh PIE2

— (5) — EEIE BCLIE — — CCP2IE -r-0 0--0 23

8Eh PCON

— — — — — — POR BOR ---- --qq 25

8Fh — Unimplemented — —

90h — Unimplemented — —

91h SSPCON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN

0000 0000 68

92h PR2 Timer2 Period Register

1111 1111 55

93h SSPADD Synchronous Serial Port (I

C mode) Address Register 0000 0000 73, 74

94h SSPSTAT SMP CKE D/A

PSR/WUA BF 0000 0000 66

95h — Unimplemented — —

96h — Unimplemented — —

97h — Unimplemented — —

98h TXSTA CSRC TX9 TXEN SYNC

— BRGH TRMT TX9D 0000 -010 95

99h SPBRG Baud Rate Generator Register

0000 0000 97

9Ah — Unimplemented — —

9Bh — Unimplemented — —

9Ch — Unimplemented — —

9Dh — Unimplemented — —

9Eh ADRESL A/D Result Register Low Byte

xxxx xxxx 116

9Fh ADCON1 ADFM

— — — PCFG3 PCFG2 PCFG1 PCFG0 0--- 0000 112

TABLE 2-1: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Value on:

POR,

BOR

Details

page:

Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as '0', r = reserved.

Shaded locations are unimplemented, read as ‘0’.

Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose

contents are transferred to the upper byte of the program counter.

2: Bits PSPIE and PSPIF are reserved on PIC16F873/876 devices; always maintain these bits clear.

3: These registers can be addressed from any bank.

4: PORTD, PORTE, TRISD, and TRISE are not physically implemented on PIC16F873/876 devices; read as ‘0’.

5: PIR2<6> and PIE2<6> are reserved on these devices; always maintain these bits clear.

 2001 Microchip Technology Inc. DS30292C-page 17

PIC16F87X

Bank 2

100h

(3)

INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 27

101h TMR0 Timer0 Module Register

xxxx xxxx 47

102h

(3)

PCL Program Counter’s (PC) Least Significant Byte 0000 0000 26

103h

(3)

STATUS IRP RP1 RP0 TO PD ZDCC0001 1xxx 18

104h

(3)

FSR Indirect Data Memory Address Pointer xxxx xxxx 27

105h — Unimplemented — —

106h PORTB PORTB Data Latch when written: PORTB pins when read

xxxx xxxx 31

107h — Unimplemented — —

108h — Unimplemented — —

109h — Unimplemented — —

10Ah

(1,3)

PCLATH — — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 26

10Bh

(3)

INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 20

10Ch EEDATA EEPROM Data Register Low Byte

xxxx xxxx 41

10Dh EEADR EEPROM Address Register Low Byte

xxxx xxxx 41

10Eh EEDATH

— — EEPROM Data Register High Byte xxxx xxxx 41

10Fh EEADRH

— — — EEPROM Address Register High Byte xxxx xxxx 41

Bank 3

180h

(3)

INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 27

181h OPTION_REG RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0

1111 1111 19

182h

(3)

PCL Program Counter (PC) Least Significant Byte 0000 0000 26

183h

(3)

STATUS IRP RP1 RP0 TO PD ZDCC0001 1xxx 18

184h

(3)

FSR Indirect Data Memory Address Pointer xxxx xxxx 27

185h — Unimplemented — —

186h TRISB PORTB Data Direction Register

1111 1111 31

187h — Unimplemented — —

188h — Unimplemented — —

189h — Unimplemented — —

18Ah

(1,3)

PCLATH — — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 26

18Bh

(3)

INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 20

18Ch EECON1 EEPGD

— — — WRERR WREN WR RD x--- x000 41, 42

18Dh EECON2 EEPROM Control Register2 (not a physical register)

---- ---- 41

18Eh — Reserved maintain clear 0000 0000 —

18Fh — Reserved maintain clear 0000 0000 —

TABLE 2-1: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Value on:

POR,

BOR

Details

page:

Legend:

x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as '0', r = reserved.

Shaded locations are unimplemented, read as ‘0’.

Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose

contents are transferred to the upper byte of the program counter.

2: Bits PSPIE and PSPIF are reserved on PIC16F873/876 devices; always maintain these bits clear.

3: These registers can be addressed from any bank.

4: PORTD, PORTE, TRISD, and TRISE are not physically implemented on PIC16F873/876 devices; read as ‘0’.

5: PIR2<6> and PIE2<6> are reserved on these devices; always maintain these bits clear.

PIC16F87X

DS30292C-page 18  2001 Microchip Technology Inc.

2.2.2.1 STATUS Register

The STATUS register contains the arithmetic status of

the ALU, the RESET status and the bank select bits for

data memory.

The STATUS register can be the destination for any

instruction, as with any other register. If the STATUS

the Z, DC or C bits, then the write to these three bits is

disabled. These bits are set or cleared according to the

device logic. Furthermore, the TO

and PD bits are not

writable, therefore, the result of an instruction with the

STATUS register as destination may be different than

intended.

For example, CLRF STATUS will clear the upper three

bits and set the Z bit. This leaves the STATUS register

as 000u u1uu (where u = unchanged).

It is recommended, therefore, that only BCF, BSF,

SWAPF and MOVWF instructions are used to alter the

STATUS register, because these instructions do not

affect the Z, C or DC bits from the STATUS register. For

other instructions not affecting any status bits, see the

“Instruction Set Summary."

Note: The C and DC bits operate as a borrow

and digit borrow bit, respectively, in sub-

traction. See the SUBLW and SUBWF

instructions for examples.

R/W-0 R/W-0 R/W-0 R-1 R-1 R/W-x R/W-x R/W-x

IRP RP1 RP0 TO

PD ZDCC

bit 7 bit 0

bit 7 IRP: Register Bank Select bit (used for indirect addressing)

1 = Bank 2, 3 (100h - 1FFh)

0 = Bank 0, 1 (00h - FFh)

bit 6-5 RP1:RP0: Register Bank Select bits (used for direct addressing)

11 = Bank 3 (180h - 1FFh)

10 = Bank 2 (100h - 17Fh)

01 = Bank 1 (80h - FFh)

00 = Bank 0 (00h - 7Fh)

Each bank is 128 bytes

bit 4 TO

: Time-out bit

1 = After power-up, CLRWDT instruction, or SLEEP instruction

0 = A WDT time-out occurred

bit 3 PD

: Power-down bit

1 = After power-up or by the CLRWDT instruction

0 = By execution of the SLEEP instruction

bit 2 Z: Zero bit

1 = The result of an arithmetic or logic operation is zero

0 = The result of an arithmetic or logic operation is not zero

bit 1 DC: Digit carry/borrow

bit (ADDWF, ADDLW,SUBLW,SUBWF instructions)

(for borrow, the polarity is reversed)

1 = A carry-out from the 4th low order bit of the result occurred

0 = No carry-out from the 4th low order bit of the result

bit 0 C: Carry/borrow

bit (ADDWF, ADDLW,SUBLW,SUBWF instructions)

1 = A carry-out from the Most Significant bit of the result occurred

0 = No carry-out from the Most Significant bit of the result occurred

Note: For borrow

, the polarity is reversed. A subtraction is executed by adding the two’s

complement of the second operand. For rotate (RRF, RLF) instructions, this bit is

loaded with either the high, or low order bit of the source register.

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown

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