EFM32G微控制器参考手册：业界最低能耗微控制器系列

5星 · 超过95%的资源需积分: 10 141 浏览量更新于2024-07-23 收藏 7.4MB PDF 举报

EFM32G 参考手册作为一名 IT 行业大师，我将为您生成相关的知识点，基于提供的文件信息。 **EFM32G 微控制器概述** EFM32G 是一款基于 ARM Cortex-M3 处理器的 32 位微控制器，频率高达 32MHz。它具有出色的性能和超低功耗特性，在运行模式下功耗仅为 180µA/MHz，而在睡眠模式下功耗仅为 900nA。 **关键特性** * 高性能：基于 ARM Cortex-M3 处理器，频率高达 32MHz * 超低功耗：运行模式下功耗仅为 180µA/MHz，睡眠模式下功耗仅为 900nA * 高存储容量：最高 128KB 闪存和 16KB RAM * Energy efficient 和 autonomous peripherals * Ultralow power energy modes with Sub-µ operation * 快速唤醒时间：仅需 2µs **EFM32G 微控制器系列** EFM32G 微控制器系列是目前市场上最 energy-friendly 的微控制器之一，具有出色的性能和超低功耗特性。该系列微控制器适合各种应用场景，包括工业控制、医疗设备、消费电子等。 **典型应用** EFM32G 微控制器系列非常适合以下应用： * 工业控制：工业自动化、机器人控制等 * 医疗设备：医疗仪器、健康监测设备等 * 消费电子：智能家居、可穿戴设备等 ** Gecko 系列** Gecko 系列是 EFM32G 微控制器系列的一部分，具有出色的性能和超低功耗特性。该系列微控制器非常适合需要高性能和低功耗的应用场景。 ** Energy Friendly** EFM32G 微控制器系列是目前市场上最 energy-friendly 的微控制器之一，具有出色的性能和超低功耗特性。该系列微控制器非常适合各种应用场景，包括工业控制、医疗设备、消费电子等。 **总结** EFM32G 参考手册提供了 EFM32G 微控制器系列的详细信息，包括关键特性、应用场景和技术参数。该手册是开发者和工程师的必备参考资料，可以帮助他们更好地了解和使用 EFM32G 微控制器系列。 **重要概念** * ARM Cortex-M3 处理器 * Energy efficient * Autonomous peripherals * Ultralow power energy modes * Fast wake-up time * Gecko 系列 * Energy Friendly **相关技术** * 微控制器 * 嵌入式系统 * ARM 处理器 * 低功耗设计 * 高性能计算

...the world's most energy friendly microcontrollers

2011-04-12 - d0001_Rev1.10 16

www.energymicro.com

Table 5.1. Memory System Core Peripherals

Core peripherals

Address range Peripheral

0x400E0400 – 0x41FFFFFF Reserved

0x400E0000 – 0x400E03FF AES

0x400CC400 – 0x400FFFFF Reserved

0x400CC000 – 0x400CC3FF PRS

0x400CA400 – 0x400CBFFF Reserved

0x400CA000 – 0x400CA3FF RMU

0x400C8400 – 0x400C9FFF Reserved

0x400C8000 – 0x400C83FF CMU

0x400C6400 – 0x400C7FFF Reserved

0x400C6000 – 0x400C63FF EMU

0x400C4000 – 0x400C5FFF Reserved

0x400C2000 – 0x400C3FFF DMA

0x400C0400 – 0x400C1FFF Reserved

0x400C0000 – 0x400C03FF MSC

Table 5.2. Memory System Low Energy Peripherals

Low energy peripherals

Address range Peripheral

0x4008A400 – 0x400BFFFF Reserved

0x4008A000 – 0x4008A3FF LCD

0x40088400 – 0x40089FFF Reserved

0x40088000 – 0x400883FF WDOG

0x40086C00 – 0x40087FFF Reserved

0x40086800 – 0x40086BFF PCNT2

0x40086400 – 0x400867FF PCNT1

0x40086000 – 0x400863FF PCNT0

0x40084800 – 0x40085FFF Reserved

0x40084400 – 0x400847FF LEUART1

0x40084000 – 0x400843FF LEUART0

0x40082400 – 0x40083FFF Reserved

0x40082000 – 0x400823FF LETIMER0

0x40080400 – 0x40081FFF Reserved

0x40080000 – 0x400803FF RTC

...the world's most energy friendly microcontrollers

2011-04-12 - d0001_Rev1.10 18

www.energymicro.com

5.2.3.2 Access Performance

The Bus Matrix is a multi-layer energy optimized AMBA AHB compliant bus with an internal bandwidth

of 4x a single AHB interface.

The Bus Matrix accepts new transfers to be initiated by each master in each cycle without inserting any

wait-states. However, the slaves may insert wait-states depending on their internal throughput and the

clock frequency.

The Cortex-M3 and the DMA Controller, and the peripherals (not peripherals in the low frequency clock

domain) run on clocks which can be prescaled separately. When accessing a peripheral which runs on

a frequency equal to or faster than the HFCORECLK, the number of wait cycles per access, in addition

to master arbitration, is given by:

Memory Wait Cycles with Clock Equal or Faster than the HFCORECLK

cycles

= 2 + N

slave cycles

(5.3)

where N

slave cycles

is the wait cycles introduced by the slave.

When accessing a peripheral which runs on a slower clock than the HFCORECLK, wait cycles are

introduced to allow the transfer to complete on the peripheral clock. The number of wait cycles per

access, in addition to master arbitration, is given by:

Memory Wait Cycles with Clock Slower than the CPU

cycles

= (2 + N

slave cycles

) x f

HFCORECLK

HFPERCLK

(5.4)

where N

slave cycles

is the wait cycles introduced by the slave.

Clocks and prescaling are described in more detail in Chapter 11 (p. 92) .

5.3 Access to Low Energy Peripherals (Asynchronous Registers)

5.3.1 Introduction

The Low Energy Peripherals are capable of running when the high frequency oscillator and core system

is powered off, i.e. in energy mode EM2 and in some cases also EM3. This enables the peripherals to

perform tasks while the system energy consumption is minimal.

The Low Energy Peripherals are:

• Liquid Crystal Display driver - LCD

• Low Energy Timer - LETIMER

• Low Energy UART - LEUART

• Pulse Counter - PCNT

• Real Time Counter - RTC

• Watchdog - WDOG

All Low Energy Peripherals are memory mapped, with automatic data synchronization. Because the Low

Energy Peripherals are running on clocks asynchronous to the core clock, there are some constraints

on how register accesses are performed, as described in the following sections.

5.3.1.1 Writing

Every Low Energy Peripheral has one or more registers with data that needs to be synchronized

into the Low Energy clock domain to maintain data consistency and predictable operation. Due to

...the world's most energy friendly microcontrollers

2011-04-12 - d0001_Rev1.10 19

www.energymicro.com

synchronization, the write operation requires 3 positive edges of the clock of the Low Energy Peripheral

being accessed. Such registers are marked "Asynchronous" in their description header.

See Figure 5.3 (p. 19) for an overview of the writing operation.

After writing data to a register which value is to be synchronized into the Low Energy clock domain, a

corresponding busy flag in the <module_name>_SYNCBUSY register (e.g. RTC_SYNCBUSY) is set.

This flag is set as long as synchronization is in progress and is cleared upon completion.

Note

Subsequent writes to the same register before the corresponding busy flag is cleared is not

supported. Write before the busy flag is cleared may result in undefined behavior.

In general the SYNCBUSY register only needs to be observed if there is a risk of multiple

write access to a register (which must be prevented). It is not required to wait until the

relevant flag in the SYNCBUSY register is cleared after writing a register. E.g can EM2 be

entered directly after writing a register.

Figure 5.3. Write operation to Low Energy Peripherals

Synchronizer 0

Synchronizer 1

Synchronizer n

Write[0:n]

Syncbusy Register 0

Syncbusy Register 1

Syncbusy Register n

Set 0

Set 1

Set n

Freeze

Synchronization Done

Clear 0

Clear 1

Clear n

Core Clock

Low Frequency Clock Low Frequency Clock

Core Clock Dom ain Low Frequency Clock Dom ain

5.3.1.2 Reading

When reading from a Low Energy Peripheral, the data read is synchronized regardless if it originates

in the Low Energy clock domain or core clock domain. Registers which are updated/ maintained by the

Low Energy Peripheral are read directly from the Low Energy clock domain. Registers which originate in

the core clock domain, are read from the core clock domain. See Figure 5.4 (p. 20) for an overview

of the reading operation.

Note

Writing a register and then immediately reading the new value of the register may give the

impression that the write operation is complete. This may not be the case. Please refer

to the SYNCBUSY register for correct status of the write operation to the Low Energy

Peripheral.

剩余466页未读，继续阅读

huds03

粉丝: 0
资源: 3

EFM32G微控制器参考手册：业界最低能耗微控制器系列

EFM32G开发文档中文版官方指南

超低功耗EFM32G微控制器：Cortex-M3性能与节能革命

突破节能极限：EFM32G系列微控制器——高性能与超低功耗的完美结合

efm32g-datasheet-cn_EFM32官网_EFM32_

efm32g230_datasheet.pdf

d0034_efm32tg_reference_manual

efm32_letimer_efm32_letimer_EFM32PWM_motherexg_stageqkd_EFM32_

EFM32.rar_EFM 32开发_EFM32_EFM头文件_G280F128_efm

EFM32-ADC.zip_EFM32_EFM32 ADC_efm32 ADC0_SINGLE

efm8bb1-datasheet_EFM8SBDatasheet_EFM8_

最新资源