ATmega128A微控制器数据手册

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"ATmega128A.pdf 是Atmel公司的一款高性能、低功耗的AVR系列8位微控制器的数据手册。" ATmega128A是一款基于高级精简指令集(RISC)架构的微处理器，它具备以下关键特性： 1. 高性能，低功耗：ATmega128A设计用于在执行复杂任务时保持高效的能源效率，适用于需要长时间运行且对电源需求敏感的应用。 2. 强大的指令集：该微控制器拥有133条强大指令，其中大部分指令可在单个时钟周期内执行，显著提高了处理速度。 3. 工作寄存器与外围控制寄存器：包含32个8位通用工作寄存器以及额外的外围控制寄存器，提供丰富的数据处理能力。 4. 全静态操作：能够在任何频率下工作，无需外部时钟振荡器，这使得系统设计更加灵活。 5. 高速度：在16MHz的时钟频率下，能达到16 MIPS（每秒百万指令）的吞吐量，内置的2周期乘法器进一步增强了计算性能。 6. 非易失性内存：包括128KB的在系统自编程闪存程序存储器、4KB EEPROM和4KB内部SRAM。闪存和EEPROM分别有10,000次和100,000次的写/擦除循环，确保了数据的长期保存，即使在极端环境下也能保持20年（85°C）至100年（25°C）的数据保留。 7. 可选的引导代码段：具有独立的锁定位，允许在系统编程时设置特定区域的访问权限。 8. 在系统编程(ISP)：通过芯片内的引导程序支持在线编程，且支持真正的读写同时操作。此外，还可以扩展高达64KB的外部内存空间。 9. 安全特性：编程锁定功能为软件安全提供了保障，通过SPI接口实现ISP。 10. JTAG接口：遵循IEEE std. 1149.1标准，具备边界扫描能力，以及广泛的片上调试支持。JTAG接口可用于通过JTAG接口编程闪存、EEPROM、熔丝和锁定位。 11. 外设特性：包括两个8位定时器/计数器，每个都有单独的预分频器，可以用于多种应用，如脉冲测量、定时和中断驱动等功能。 ATmega128A是一款功能强大的微控制器，广泛应用于嵌入式系统、工业控制、智能家居设备和各种IOT应用，其丰富的外设和高效能使其成为设计者的首选。

8151H–AVR–02/11

ATmega128A

in order to execute the interrupt handling routine, and hardware clears the corresponding inter-

rupt flag. Interrupt flags can also be cleared by writing a logic one to the flag bit position(s) to be

cleared. If an interrupt condition occurs while the corresponding interrupt enable bit is cleared,

the interrupt flag will be set and remembered until the interrupt is enabled, or the flag is cleared

by software. Similarly, if one or more interrupt conditions occur while the global interrupt enable

bit is cleared, the corresponding interrupt flag(s) will be set and remembered until the global

interrupt enable bit is set, and will then be executed by order of priority.

The second type of interrupts will trigger as long as the interrupt condition is present. These

interrupts do not necessarily have interrupt flags. If the interrupt condition disappears before the

interrupt is enabled, the interrupt will not be triggered.

When the Atmel

AVR

exits from an interrupt, it will always return to the main program and exe-

cute one more instruction before any pending interrupt is served.

Note that the Status Register is not automatically stored when entering an interrupt routine, nor

restored when returning from an interrupt routine. This must be handled by software.

When using the CLI instruction to disable interrupts, the interrupts will be immediately disabled.

No interrupt will be executed after the CLI instruction, even if it occurs simultaneously with the

CLI instruction. The following example shows how this can be used to avoid interrupts during the

timed EEPROM write sequence.

When using the SEI instruction to enable interrupts, the instruction following SEI will be exe-

cuted before any pending interrupts, as shown in this example.

Assembly Code Example

in r16, SREG ; store SREG value

cli ; disable interrupts during timed sequence

sbi EECR, EEMWE ; start EEPROM write

sbi EECR, EEWE

out SREG, r16 ; restore SREG value (I-bit)

C Code Example

char cSREG;

cSREG = SREG; /* store SREG value */

/* disable interrupts during timed sequence */

__disable_interrupt();

EECR |= (1<<EEMWE); /* start EEPROM write */

EECR |= (1<<EEWE);

SREG = cSREG; /* restore SREG value (I-bit) */

8151H–AVR–02/11

ATmega128A

7.2 SRAM Data Memory

The Atmel

AVR

ATmega128A supports two different configurations for the SRAM data memory

as listed in Table 7-1.

Figure 7-2 shows how the ATmega128A SRAM Memory is organized.

The ATmega128A is a complex microcontroller with more peripheral units than can be sup-

ported within the 64 location reserved in the Opcode for the IN and OUT instructions. For the

Extended I/O space from $60 - $FF in SRAM, only the ST/STS/STD and LD/LDS/LDD instruc-

tions can be used. The Extended I/O space does not exist when the ATmega128A is in the

ATmega103 compatibility mode.

In normal mode, the first 4352 Data Memory locations address both the Register file, the I/O

Memory, Extended I/O Memory, and the internal data SRAM. The first 32 locations address the

memory, and the next 4096 locations address the internal data SRAM.

In ATmega103 compatibility mode, the first 4096 Data Memory locations address both the Reg-

ister file, the I/O Memory and the internal data SRAM. The first 32 locations address the Register

file, the next 64 location the standard I/O memory, and the next 4000 locations address the inter-

nal data SRAM.

An optional external data SRAM can be used with the ATmega128A. This SRAM will occupy an

area in the remaining address locations in the 64K address space. This area starts at the

address following the internal SRAM. The Register file, I/O, Extended I/O and Internal SRAM

occupies the lowest 4352bytes in normal mode, and the lowest 4096bytes in the ATmega103

compatibility mode (Extended I/O not present), so when using 64 Kbytes (65536bytes) of Exter-

nal Memory, 61184Bytes of External Memory are available in normal mode, and 61440Bytes in

ATmega103 compatibility mode. See “External Memory Interface” on page 22 for details on how

to take advantage of the external memory map.

When the addresses accessing the SRAM memory space exceeds the internal data memory

locations, the external data SRAM is accessed using the same instructions as for the internal

data memory access. When the internal data memories are accessed, the read and write strobe

pins (PG0

and PG1) are inactive during the whole access cycle. External SRAM operation is

enabled by setting the SRE bit in the MCUCR Register.

Accessing external SRAM takes one additional clock cycle per byte compared to access of the

internal SRAM. This means that the commands LD, ST, LDS, STS, LDD, STD, PUSH, and POP

take one additional clock cycle. If the Stack is placed in external SRAM, interrupts, subroutine

calls and returns take three clock cycles extra because the two-byte program counter is pushed

and popped, and external memory access does not take advantage of the internal pipe-line

memory access. When external SRAM interface is used with wait-state, one-byte external

access takes two, three, or four additional clock cycles for one, two, and three wait-states

respectively. Interrupts, subroutine calls and returns will need five, seven, or nine clock cycles

more than specified in the instruction set manual for one, two, and three wait-states.

Table 7-1. Memory Configurations

Configuration Internal SRAM Data Memory External SRAM Data Memory

Normal mode 4096 up to 64K

ATmega103 Compatibility

mode

4000 up to 64K

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ATmega128A微控制器数据手册

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