Maryland大学内存系统模拟器DRAMSim详解

需积分: 31 84 浏览量更新于2024-07-30 1 收藏 500KB PDF 举报

"DRAMSim是来自University of Maryland的内存系统模拟器，专用于精确仿真内存时钟行为。该手册提供对模拟内存系统的详细介绍，包括其组成、基本假设和模拟框架。" 在深入理解DRAMSim之前，首先要明确的是，DRAM（动态随机存取存储器）是计算机系统中广泛使用的主内存类型，它负责存储临时数据。DRAMSim作为一个内存仿真工具，对于系统设计者和研究人员来说至关重要，因为它允许他们在实际硬件制造之前分析和优化内存子系统的性能。该模拟器由三个主要部分构成：总线接口单元（BIU）、一个或多个事务驱动的内存控制器以及一个或多个命令驱动的内存系统。BIU是处理器与内存控制器之间的通信桥梁，内存控制器则负责管理和调度内存访问请求，而命令驱动的内存系统则模拟真实的DRAM行为。如手册中所述，内存交易的生命周期涉及到三个独立的实体：处理器、内存控制器和DRAM内存系统。这些实体都被视为独立时钟同步状态机，运行在不同的时钟域中。在当前的实现中，有两个主要的时钟域——CPU时钟域和DRAM内存系统时钟域。例如，FB-DIMM（前端总线双列直插式内存模块）是一种特定类型的内存模块，它使用了分离的内存控制器和独立的时钟系统来提高系统带宽和性能。在DRAMSim中，用户会接触到术语如“事务驱动”和“命令驱动”，这指的是内存访问的不同处理方式。事务驱动内存控制器根据来自处理器的请求进行操作，而命令驱动内存系统则是根据预定义的命令序列执行操作，这些命令可能包括读、写、刷新等。手册还会详细解释模拟的基本假设，比如内存访问延迟、带宽限制、内存层次结构以及不同内存技术的特性。此外，它还提供了关于如何配置和使用DRAMSim进行仿真，以及如何解读和分析仿真结果的指导。通过使用DRAMSim，开发者可以测试不同内存配置对系统整体性能的影响，如内存大小、频率、带宽和拓扑结构。这有助于他们在设计阶段就优化系统，避免潜在的性能瓶颈，从而提升整个计算平台的效率。 DRAMSim是一个强大的工具，它允许用户在不涉及物理硬件的情况下，对内存系统进行详尽的性能分析和优化，这对于现代高性能计算和数据中心设计具有重大意义。

UNIVERSITY OF MARYLAND MEMORY SYSTEM SIMULATOR MANUAL – 5

depending on design, the channel ID or rank ID can be mapped to the low order address bit to obtain the most bank

parallelism, but in memory systems that allow end users to flexibly configure the memory system by adding more ranks

or changing channel configurations, the channel ID and rank ID’s are typically mapped to the high order address bits.

.Figure 4 demonstrates the device configuration of a specific 256 Mbit SDRAM device. Figure 4 shows that a

256 Mbit SDRAM device may be shipped in one of three different configurations: 64 Mbit x 4, 32 Mbit x 8, and 16

Mbit x 16. Basically, the same 256 Mbit device could contain 64 million uniquely addressable locations with each

location being 4 bit wide, 32 million uniquely addressable 8 bit wide locations, or 16 million uniquely addressable 16 bit

wide locations. However, many modern memory systems use 64 bit wide data busses, so in this case, multiple DRAM

devices are then combined to form the 64 bit wide data bus. The effect of these different configurations is that there are

different numbers of columns per “DRAM page” for each configuration.

Due to the variable sizes and configuration of the memory devices used in memory systems, address mapping

differs with each configuration. One difficulty related to the precise definition of an address mapping scheme is that in a

memory system with differently configured memory modules, the mapping scheme must differ from module to module.

In figure 5, one memory address mapping scheme with 256 Mbit SDRAM devices and uniform configuration of the

memory system is assumed. In this figure there are 4 ranks of memory modules, each module formed from 16 bit wide

256 Mbit SDRAM devices. In this configuration, the 16 bit wide Mbit devices use 9 bits for column addressing, 2 bits to

Device config 64 Meg x 4 32 Meg x 8 16 Meg x 16

Configuration 16 M x 4 x 4 bks 8 M x 8 x 4 bks 4 M x 16 x 4 bks

row addressing 8K (A0 - A12) 8K (A0 - A12) 8K (A0 - A12)

bank addressing 4 (BA0, BA1) 4 (BA0, BA1) 4 (BA0, BA1)

col addressing 2K(A0-A9,A11) 1K (A0-A9) 512 (A0- A8)

8 of the x8 devices

form 64 bit wide

data bus

4 of the x16 devices

form 64 bit wide

data bus

“DRAM page size” differs with different configurations.

Fig. 4: Different Configurations of a 256 Mbit DRAM device

Device config 16 Meg x 16

Configuration 4 M x 16 x 4 bks

row addressing 8K (A0 - A12)

bank addressing 4 (BA0, BA1)

col addressing 512 (A0- A8)

32 bit physical address (byte addressable)

memory

rank

bank

column

row

not

used

Fig. 5: Open Page Address Mapping Scheme of a 512 MB system with 256 Mbit DRAM devices

UNIVERSITY OF MARYLAND MEMORY SYSTEM SIMULATOR MANUAL – 6

address 4 different banks, 13 bits to address 8192 rows, and 2 bits to address 4 ranks of memory. Altogether, 29 bits of

physical address is used here to address 512 Megabyte of memory. The address mapping policy illustrated in figure 5 is

optimized for an open page memory system, since the column ID’s are mapped to the lowest order bits, and multiple

accesses to the same array of memory would most likely be mapped to different columns within the saw row and same

bank of DRAM devices. Alternative memory address mapping schemes may achieve a higher degrees of performance

depending on the configuration and row buffer management policy. Finally, the memory addressing scheme presented in

figure 5 is specified for a single channel of memory. Multi-channel memory require an address mapping policy that can

adequately distribute the memory accesses to different channels.

D.BASIC TIMING PARAMETERS

In any DRAM memory-access protocol, a set of timing parameters is used to characterize various command

durations and latencies. Although the exacting desciption of a full and complete protocol requires the use of tens of

different timing parameters, a generic protocol can be well described with a subset of the timing parameters. The timing

parameters used in the simulation framework are summarized in table 1

Parameter Description Illust.

Burst

Data Burst duration. Time period that data burst occupies on the data bus. Typically 4 or 8 beats of

data. In DDR SDRAM, 4 beats of data occupies 2 full cycles. Also known as t

figure 7

CAS

Column Access Strobe latency. Time interval between column access command and data return by

DRAM device(s). Also known as t

figure 7

CMD

Command transport duration. Time period that a command occupies on the command bus as it is

transported from the DRAM controller to the DRAM devices.

figure 6

CWD

Column Write Delay. Time interval between issuance of column write command and placement of

data on data bus by the DRAM controller.

figure 7

DQS

Data Strobe turnaround. Used in DDR and DDR2 SDRAM memory systems. Not used in SDRAM

or Direct RDRAM memory systems. 1 full cycle in DDR SDRAM systems.

figure 12

FAW

Four bank Activation Window. A rolling time frame in which a maximum of four bank activation

may be engaged. Limits peak current profile.

figure 16

RAS

Row Access Strobe. Time interval between row access command and data restoration in DRAM

array. After t

RAS

, DRAM bank could be precharged.

figure 6

Row Cycle. Time interval between accesses to different rows in same bank

= t

RAS

+ t

figure 7

RCD

Row to Column command Delay. Time interval between row access command and data ready at

sense amplifiers.

figure 6

RFC

Refresh Cycle. Time between refresh commands or refresh command and row activation. figure 10

RRD

Row activation to Row activation Delay. Minimum time interval between two row activation

commands to same DRAM device. Limits peak current profile.

figure 15

Row Precharge. Time interval that it takes for a DRAM array to be precharged and readied for

another row access.

figure 9

Write Recovery time. Minimum time interval between end of write data burst and the start of a

precharge command. Allows sense amplifiers to restore data to cells

figure 8

Table 1: Summary of DRAM Timing Parameters

剩余25页未读，继续阅读

树袋大熊

粉丝: 34
资源: 7

Maryland大学内存系统模拟器DRAMSim详解

hybrid-memory-simulator:混合内存模拟器由MarssX86，DRAMSim2，NVMain和Hybridsim组成。 该模拟器已经提供了插件DRAMSim2NVMainHybridsim的接口作为主存储器以及与该接口有关的补丁。 您可以使用模拟器来模拟混合内存系统

PIMSim:PIMSim是一种内存中仿真器，具有GEM5完整系统仿真的兼容性

dramsim2模拟器

user manual_manual_

snort_manual.rar_linux manual_snort_manual

eRemote Manual_usermanual_

manual_2_manual_

manual_1_manual_

OpenGL Reference Manual OpenGL Reference Manual

PSAT-Manual.rar_pca_psat_psat manual_psat_manual

最新资源

hybrid-memory-simulator:混合内存模拟器由MarssX86，DRAMSim2，NVMain和Hybridsim组成。该模拟器已经提供了插件DRAMSim2NVMainHybridsim的接口作为主存储器以及与该接口有关的补丁。您可以使用模拟器来模拟混合内存系统