FPGA安全现状：实施与攻击分析

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"这篇文章‘Security on FPGAs：State of the Art Implementations and Attacks’深入探讨了嵌入式系统中的安全问题，特别是聚焦在FPGA（Field-Programmable Gate Array，现场可编程门阵列）上的安全挑战。随着FPGA在嵌入式系统中的广泛应用，确保其整体安全性变得至关重要。作者Thomas Wollinger、Jorge Guajardo和Christof Paar来自通信安全组（COSY）- 鲁尔大学波鸿分校和英飞凌科技公司的安全移动解决方案部门，他们提供了当前关于FPGA安全性的最新研究概述。文章指出，由于许多嵌入式应用的无线特性以及它们在日常生活中的普遍存在，安全和隐私保护机制的需求日益增强。FPGA因其可重构性在加密应用中具有显著优势，但同时也暴露出潜在的安全问题。作者讨论了这些问题，并列出了当前FPGA安全研究中待解决的关键问题。文章详细介绍了FPGA上公开密钥和对称密钥算法的实现情况，这些实现对于理解FPGA在安全领域的潜力和局限性至关重要。通过对现有安全措施的分析，读者可以了解到FPGA在设计和实现层面可能遇到的安全威胁，例如硬件木马、侧信道攻击、IP盗用等。此外，文章还涉及了FPGA在安全领域的未来研究方向，包括但不限于如何提高FPGA的抗攻击能力、开发更安全的硬件架构以及如何通过设计优化来减少潜在的攻击表面。这为研究人员和工程师提供了宝贵的参考，帮助他们在设计和实施FPGA系统时充分考虑安全因素，以应对不断演变的网络安全威胁。总结来说，这篇综述文章对于了解FPGA安全的现状、存在的问题以及未来的研究趋势提供了全面的洞察，对于从事嵌入式系统、密码学和硬件安全研究的人员来说是不可或缺的参考资料。" 关键词: 算法设计、性能、安全、FPGA、加密应用、安全问题、研究问题、公开密钥算法、对称密钥算法。

Cryptography on FPGAs: State of the Art Implementations and Attacks · 7

3.2 Black Box Attack

The classical method to reverse engineer a chip is the so called Black Box attack.

The attacker inputs all possible combinations, while saving the corresp onding out-

puts. The intruder is then able to extract the inner logic of the FPGA, with the

help of the Karnaugh map or algorithms that simplify the resulting tables. This

attack is only feasible if a small FPGA with explicit inputs and outputs is attacked

and a lot of processor power is available. The reverse engineering eﬀort grows and

it will become less feasible as the size and complexity of the FPGA increases. The

cost of the attack, furthermore, rises with the usage of state machines, LFSRs (Lin-

ear Feedback Shift Registers), integrated storage, and, if pins can be used, input

and output [Dipert 2000].

3.3 Readback Attack

Readback is a feature that is provided for most FPGA families. This feature allows

to read a conﬁguration out of the FPGA for easy debugging. An overview of the

attack is given in [Dipert 2000]. The idea of the attack is to read the conﬁguration

of the FPGA through the JTAG or programming interface in order to obtain secret

information (e.g. keys, proprietary algorithm). The readback functionality can be

prevented with a security bit. In some FPGA families, more than one bit is used

to disable diﬀerent features, e.g., the JTAG boundary. In [Aplan et al. 1999], the

idea of using a security antifuse to prevent readout of information is patented.

However, it is conceivable, that an attacker can overcome these countermeasures

in FPGA with fault injection. This kind of attack was ﬁrst introduced in [Boneh

et al. 1997]. The authors showed how to break public-key algorithms, such as the

RSA and Rabin signature schemes, by exploiting hardware faults. Furthermore,

they give a high level description of transient faults, latent faults, and induced

faults. This publication, was followed by [Biham and Shamir 1997], where the au-

thors introduced diﬀerential fault analysis, which can potentially be applied against

all symmetric algorithms in the open literature. Meanwhile there have been many

publications that show diﬀerent techniques to insert faults, e.g., electro magnetic

radiation [Quisquater and Samyde 2001], infrared laser [Ajluni 1995], or even a ﬂash

light [Skorobogatov and Anderson 2002]. It seems very likely that these attacks can

be easily applied to FPGAs, since they are not especially targeted to ASICs. There-

fore, one is able to deactivate security bits and/or the countermeasures, resulting in

the ability to read out the conﬁguration of the FPGA [Kessner 2000; Dipert 2000].

Despite these attacks Actel Corporation [Actel Corporation 2002] claims that

after the programming phase, the cells of FPGAs cannot be read at all. On the

other hand Xilinx oﬀers the users the software tool JBits [Guccione and Levi ],

which provides an API to access the bitstream information and allows dynamic

reconﬁguration for Xilinx Virtex FPGAs. JBits allows a simpliﬁed and automated

access to speciﬁc part of the bitstream, resulting in a extra advantage for the

attacker who performs a readback attack.

3.4 Cloning of SRAM FPGAs

The security implications that arise in a system that uses SRAM FPGAs are ob-

vious, if the conﬁguration data is stored unprotected in the system but external to

the FPGA. In a standard scenario, the conﬁguration data is stored externally in

ACM Special Issue Security and Embedded Systems Vol. No. March 2003.

8 · Thomas Wollinger et al.

nonvolatile memory (e.g., PROM) and is transmitted to the FPGA at power up

in order to conﬁgure the FPGA. An attacker could easily eavesdrop on the trans-

mission and get the conﬁguration ﬁle. This attack is therefore feasible for large

organizations as well as for those with low budgets and modest sophistication.

3.5 Reverse-Engineering of the Bitstreams

The attacks described so far output the bitstream of the FPGA design. In order

to get the design of proprietary algorithms or the secret keys, one has to reverse-

engineer the bitstream. The condition to launch the attack is not only that the

attacker has to be in possession of the bitstream, but furthermore the bitstream

has to be in the clear, meaning it is not encrypted.

FPGA manufactures claim, that the security of the bitstream relies on the dis-

closure of the layout of the conﬁguration data. This information will only be

made available if a non-disclosure agreement is signed, which is, from a crypto-

graphic point of view, an extremely insecure situation. This security-by-obscurity

approach was broken at least ten years ago when the CAD software company NEO-

Cad reverse-engineered a Xilinx FPGA. NEOCad was able to reconstruct the neces-

sary information about look-up tables, connections, and storage elements [Seamann

2000]. Hence, NEOCad was able to produce design software without signing non-

disclosure agreements with the FPGA manufacturer. Even though a big eﬀort has

to be made to reverse engineer the bitstream, for large organizations it is quite

feasible. In terms of government organizations as attackers, it is also possible that

they will get the information of the design methodology directly from the vendors

or companies that signed NDAs.

3.6 Physical Attack

The aim of a physical attack is to investigate the chip design in order to get in-

formation about proprietary algorithms or to determine the secret keys by probing

points inside the chip. Hence, this attack targets parts of the FPGA, which are not

available through the normal I/O pins. This can potentially be achieved through

visual inspections and by using tools such as optical microscopes and mechanical

probes. However, FPGAs are becoming so complex that only with advanced meth-

ods, such as Fo cused Ion Beam (FIB) systems, one can launch such an attack. To

our knowledge, there are no countermeasures to protect FPGAs against this form

of physical threat. In the following, we will try to analyze the eﬀort needed to

physically attack FPGAs manufactured with diﬀerent underlying technologies.

3.6.1 SRAM FPGAs. Unfortunately, there are no publications available that

accomplished a physical attack against SRAM FPGAs. This kind of attack is only

treated very superﬁcially in a few articles, e.g. [Richard 1998]. In the related area

of SRAM memory, however there has been a lot of eﬀort by academia and industry

to exploit this kind of attack [Gutmann 1996; 2001; Anderson and Kuhn 1997;

Williams et al. 1996; Schroder 1998; Soden and Anderson 1993; Kommerling and

Kuhn 1999]. Due to the similarities in structure of the SRAM memory cell and the

internal structure of the SRAM FPGA, it is most likely that the attacks can be

employed in this setting.

ACM Special Issue Security and Embedded Systems Vol. No. March 2003.

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