5
TCA9517-Q1
www.ti.com.cn
ZHCSIF1 –JUNE 2018
Copyright © 2018, Texas Instruments Incorporated
(1) JEDEC document JEP155 states that 500 V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250 V CDM allows safe manufacturing with a standard ESD control process.
7.2 ESD Ratings
VALUE UNIT
V
(ESD)
Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001
(1)
±5500
V
Charged-device model (CDM), per JEDEC specification JESD22-
C101
(2)
±1000
Machine model (A115-A) ±200
(1) Low-level supply voltage
(2) V
IL
specification is for the first low level seen by the SDAB and SCLB lines. V
ILc
is for the second and subsequent low levels seen by the
SDAB and SCLB lines. See V
ILC
and Pullup Resistor Sizing for V
ILC
application information
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
V
CCA
Supply voltage, A-side bus 0.9
(1)
5.25 V
V
CCB
Supply voltage, B-side bus
V
CCA
≤ V
CCB
2.7 5.25
V
V
CCA
> V
CCB
2.9 5.25
V
IH
High-level input voltage
SDAA, SCLA 0.7 × V
CCA
5.25
VSDAB, SCLB 0.7 × V
CCB
5.25
EN 0.7 × V
CCB
5.25
V
IL
Low-level input voltage
SDAA, SCLA 0.3 × V
CCA
VSDAB, SCLB
(2)
0.3 × V
CCB
EN 0.3 × V
CCB
I
OL
Low-level output current 6 mA
T
A
Operating free-air temperature –40 125 °C
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
7.4 Thermal Information
THERMAL METRIC
(1)
TCA9517-Q1
UNITDGK (VSSOP)
8 PINS
R
θJA
Junction-to-ambient thermal resistance 187.6 °C/W
R
θJC(top)
Junction-to-case (top) thermal resistance 59.3 °C/W
R
θJB
Junction-to-board thermal resistance 108.6 °C/W
ψ
JT
Junction-to-top characterization parameter 3.4 °C/W
ψ
JB
Junction-to-board characterization parameter 106.9 °C/W
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