Elpida EHD013091MA MCP: 2Gb DDR Mobile RAM + 4Gb NAND Flash Memory

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"EMTW-MT-090082(E1274E20) 4G+2G.pdf 是 Elpida 公司的一款内存数据手册，包含了高清完整的规格信息。这款产品是2Gb DDR Mobile RAM 和 4Gb NAND Flash Memory 的多芯片封装（MCP）组件，采用13.0mm x 10.5mm尺寸的137球脚FBGA封装，引脚间距为0.8mm，符合RoHS标准且不含卤素。工作环境温度范围为-25°C至+85°C。" 在这款产品中，DDR Mobile RAM 和 NAND Flash Memory 是独立工作的： DDR Mobile RAM： - 容量：2Gbits - 内部结构：16M words × 32bits × 4 banks - 电源电压：D-VDD = 1.8V ± 0.1V - 这部分详细信息可以在2Gbits DDR Mobile RAM 部分的第8页找到。DDR内存常用于移动设备，提供高速数据存储和处理，适用于手机、平板电脑等需要高性能内存的设备。 NAND Flash Memory： - 容量：4Gbits - 内部结构：256M words × 16bits - 电源电压：F-VDD = 1.7V to 1.95V - 这部分详细信息可在4Gbits NAND Flash memory 部分的第60页查看。NAND Flash是一种非易失性存储技术，常用于持久存储数据，如手机的内部存储或SD卡。 MCP（Multi-Chip Package）技术将两种不同类型的内存集成在一个封装内，减少了空间需求，提高了系统的集成度，降低了生产成本，并且简化了设计流程。这种封装方式在便携式设备中非常常见，因为它允许在有限的空间内提供更大的存储容量和更复杂的系统功能。此外，产品还强调其符合RoHS（Restriction of Hazardous Substances，限制有害物质指令）标准，意味着它不含有铅和其他有害物质，有利于环保。而无卤素特性进一步确保了产品的安全性，符合现代电子产品的环保趋势。 EMTW-MT-090082(E1274E20) 4G+2G.pdf 描述的是Elpida公司的一款高密度、高性能的移动内存解决方案，结合了高速动态随机存取内存（DDR）和大容量闪存（NAND Flash），适用于需要高效能、大容量存储的移动设备。

EHD013091MA

Preliminary Data Sheet E1274E20 (Ver. 2.0)

Pin Function

CK, /CK (input pins)

The CK and the /CK are the master clock inputs. All inputs except DMs, DQSs and DQs are referred to the cross

point of the CK rising edge and the /CK falling edge. When a read operation, DQSs and DQs are referred to the

cross point of the CK and the /CK. When a write operation, DMs and DQs are referred to the cross point of the DQS

and the VDD/2 level. DQSs for write operation are referred to the cross point of the CK and the /CK. The other input

signals are referred at CK rising edge.

/CS (input pin)

When /CS is low, commands and data can be input. When /CS is high, all inputs are ignored. However, internal

operations (bank active, burst operations, etc.) are held.

/RAS, /CAS, and /WE (input pins)

These pins define operating commands (read, write, etc.) depending on the combinations of their voltage levels.

See "Command operation".

A0 to A12 (input pins)

Row address (AX0 to AX12) is determined by the A0 to the A12 level at the cross point of the CK rising edge and the

/CK falling edge in a bank active command cycle. Column address is loaded at the cross point of the CK rising edge

and the /CK falling edge in a read or a write command cycle (See “Address Pins Table”). This column address

becomes the starting address of a burst operation.

[Address Pins Table]

Address (A0 to A12)

Page size

Organization

Row address Column address

4KB × 32 bits AX0 to AX12 AY0 to AY9

A10 (AP) (input pin)

A10 defines the precharge mode when a precharge command, a read command or a write command is issued. If

A10 = high when a precharge command is issued, all banks are precharged. If A10 = low when a precharge

command is issued, only the bank that is selected by BA1/BA0 is precharged. If A10 = high when read or write

command, auto precharge function is enabled.

BA0 and BA1 (input pins)

BA0 and BA1 are bank select signals (BA). The memory array is divided into bank 0, bank 1, bank 2 and bank 3.

(See Bank Select Signal Table)

[Bank Select Signal Table]

BA0 BA1

Bank 0 L L

Bank 1 H L

Bank 2 L H

Bank 3 H H

Remark: H: VIH. L: VIL.

EHD013091MA

Preliminary Data Sheet E1274E20 (Ver. 2.0)

Command Operation

Command Truth Table

The DDR Mobile RAM recognizes the following commands specified by the /CS, /RAS, /CAS, /WE and address pins.

CKE

Command Symbol n – 1 n /CS /RAS /CAS /WE BA1 BA0 AP Address

Ignore command DESL H H H × × × × × × ×

No operation NOP H H L H H H × × × ×

Burst stop command BST H H L H H L × × × ×

Column address and read command READ H H L H L H V V L V

Read with auto precharge READA H H L H L H V V H V

Column address and write command WRIT H H L H L L V V L V

Write with auto precharge WRITA H H L H L L V V H V

Row address strobe and bank active ACT H H L L H H V V V V

Precharge select bank PRE H H L L H L V V L ×

Precharge all bank PALL H H L L H L × × H ×

Refresh REF H H L L L H × × × ×

SELF H L L L L H × × × ×

Mode register set MRS H H L L L L L L L V

EMRS H H L L L L H L L V

Remark: H: VIH. L: VIL. ×: Don’t care V: Valid address input

Note: The CKE level must be kept for 1 CK cycle at least.

Ignore command [DESL]

When /CS is high at the cross point of the CK rising edge and the VDD/2 level, all input signals are neglected and

internal state is held.

No operation [NOP]

As long as this command is input at the cross point of the CK rising edge and the VDD/2 level, address and data

input are neglected and internal state is held.

Burst stop command [BST]

This command stops a current burst operation.

Column address strobe and read command [READ]

This command starts a read operation. The start address of the burst read is determined by the column address

(See “Address Pins Table” in Pin Function) and the bank select address. After the completion of the read operation,

all output buffers become high-Z.

Read with auto precharge [READA]

This command starts a read operation. After completion of the read operation, precharge is automatically executed.

Column address strobe and write command [WRIT]

This command starts a write operation. The start address of the burst write is determined by the column address

(See “Address Pins Table” in Pin Function) and the bank select address.

Write with auto precharge [WRITA]

This command starts a write operation. After completion of the write operation, precharge is automatically executed.

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