EFM32ZG110F32-QFN24: 能耗友好型ARM Cortex-M0+ 微控制器

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"EFM32ZG110F32-QFN24是一款基于ARM Cortex-M0+内核的微控制器（MCU），工作频率最高可达24MHz，属于EFM32ZG系列，是全球最节能的微控制器之一。" EFM32ZG系列微控制器是能量效率极高的32位产品，主要特点包括： 1. **高性能32位ARM Cortex-M0+处理器**：运行速度高达24MHz，提供了高效的处理能力，适用于对性能有需求的8位、16位和32位应用。 2. **内存配置**：具备最多32KB的闪存（Flash）和4KB的RAM，满足不同层次的存储需求。 3. **能源高效且独立的外设**：内置的外设在执行任务时能降低功耗，提高了整体系统效率。 4. **超低功耗能源模式**：在待机模式下，操作电流可低至亚微安级别，实现了极低的静态电流消耗。 5. **快速唤醒时间**：仅需2微秒即可从睡眠模式恢复到工作状态，确保了快速响应。 EFM32ZG系列在活跃和休眠模式下都具有出色的低功耗特性，运行模式下的功耗低至114µA/MHz，远超其他8位、16位和32位解决方案。其低能量消耗的优势在于： - **自主和节能的外设**：这些外设能够在不依赖主处理器的情况下工作，减少了不必要的能量浪费。 - **高度集成的芯片和模拟组件**：高集成度降低了外围电路的需求，进一步减小了系统的体积和能耗。 - **行业标准的32位ARM Cortex-M0+处理器**：结合了强大的32位处理能力和优化的能源管理，确保了高效运算的同时保持低功耗。这些特性使得EFM32ZG系列特别适合于对能源敏感的应用，如物联网(IoT)设备、穿戴式技术、电池供电系统、远程传感器和其他需要长时间运行而无需频繁更换电池的场景。其典型应用可能包括： - **环境监测**：例如温度、湿度、光照等传感器节点。 - **无线通信**：如蓝牙低功耗(BLE)设备或Zigbee网络节点。 - **便携式医疗设备**：如心率监测器、血糖仪等。 - **智能家居**：如智能插座、安全监控等。 - **能源管理**：例如智能电表和能源监测系统。 EFM32ZG系列是针对能源效率和性能寻求最佳平衡的开发者的理想选择，通过其创新的低功耗设计和强大的功能集，为各种低功耗应用提供了新的可能性。

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The embedded SRAM is located at address 0x20000000 in the memory map of the EFM32ZG. It is also

mapped in code space at address 0x10000000 to keep compatibility towards Cortex-M3 and Cortex-M4

EFM32-devices, that uses this code-space mapped SRAM for faster instruction fetching.

5.2.1 Peripherals

The peripherals are mapped into the peripheral memory segment, each with a fixed size address range

according to Table 5.1 (p. 16) , Table 5.2 (p. 16) and Table 5.3 (p. 16) .

Table 5.1. Memory System Core Peripherals

Core peripherals

Address Range Module Name

0x400E0000 - 0x400E03FF AES

0x400CA000 - 0x400CA3FF RMU

0x400C8000 - 0x400C83FF CMU

0x400C6000 - 0x400C63FF EMU

0x400C2000 - 0x400C3FFF DMA

0x400C0000 - 0x400C03FF MSC

Table 5.2. Memory System Low Energy Peripherals

Low Energy peripherals

Address Range Module Name

0x40088000 - 0x400883FF WDOG

0x40086000 - 0x400863FF PCNT0

0x40084000 - 0x400843FF LEUART0

0x40080000 - 0x400803FF RTC

Table 5.3. Memory System Peripherals

Peripherals

Address Range Module Name

0x400CC000 - 0x400CC3FF PRS

0x40010400 - 0x400107FF TIMER1

0x40010000 - 0x400103FF TIMER0

0x4000C400 - 0x4000C7FF USART1

0x4000A000 - 0x4000A3FF I2C0

0x40006000 - 0x40006FFF GPIO

0x40004000 - 0x400043FF IDAC0

0x40002000 - 0x400023FF ADC0

0x40001000 - 0x400013FF ACMP0

0x40000000 - 0x400003FF VCMP

5.2.2 Bus Matrix

The Bus Matrix connects the memory segments to the bus masters:

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• Code: CPU instruction or data fetches from the code space

• System: CPU read and write to the SRAM and peripherals

• DMA: Access to SRAM, Flash and peripherals

5.2.2.1 Arbitration

The Bus Matrix uses a round-robin arbitration algorithm which enables high throughput and low latency

while starvation of simultaneous accesses to the same bus slave are eliminated. Round-robin does not

assign a fixed priority to each bus master. The arbiter does not insert any bus wait-states.

5.2.2.2 Access Performance

The Bus Matrix is a multi-layer energy optimized AMBA AHB compliant bus with an internal bandwidth

equal to 4 times a single AHB-bus.

The Bus Matrix accepts new transfers initiated by each master in every clock cycle without inserting

any wait-states. The slaves, however, may insert wait-states depending on their internal throughput and

the clock frequency.

The Cortex-M0+, the DMA Controller, and the peripherals run on clocks that can be prescaled separately.

When accessing a peripheral which runs on a frequency equal to or faster than the HFCORECLK, the

number of wait cycles per access, in addition to master arbitration, is given by:

Memory Wait Cycles with Clock Equal or Faster than HFCORECLK

cycles

= 2 + N

slave cycles

, (5.1)

where N

slave cycles

is the wait cycles introduced by the slave.

When accessing a peripheral running on a clock slower than the HFCORECLK, wait-cycles are

introduced to allow the transfer to complete on the peripheral clock. The number of wait cycles per

access, in addition to master arbitration, is given by:

Memory Wait Cycles with Clock Slower than CPU

cycles

= (2 + N

slave cycles

) x f

HFCORECLK

HFPERCLK

, (5.2)

where N

slave cycles

is the number of wait cycles introduced by the slave.

For general register access, N

slave cycles

= 1.

More details on clocks and prescaling can be found in Chapter 11 (p. 92) .

5.3 Access to Low Energy Peripherals (Asynchronous Registers)

5.3.1 Introduction

The Low Energy Peripherals are capable of running when the high frequency oscillator and core system

is powered off, i.e. in energy mode EM2 and in some cases also EM3. This enables the peripherals to

perform tasks while the system energy consumption is minimal.

The Low Energy Peripherals are:

• Low Energy UART - LEUART

• Pulse Counter - PCNT

• Real Time Counter - RTC

• Watchdog - WDOG

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All Low Energy Peripherals are memory mapped, with automatic data synchronization. Because the Low

Energy Peripherals are running on clocks asynchronous to the core clock, there are some constraints

on how register accesses can be done, as described in the following sections.

5.3.1.1 Writing

Every Low Energy Peripheral has one or more registers with data that needs to be synchronized into

the Low Energy clock domain to maintain data consistency and predictable operation. There are two

different synchronization mechanisms on the Zero Gecko; immediate synchronization, and delayed

synchronization. Immediate synchronization is available for the RTC and results in an immediate update

of the target registers. Delayed synchronization is used for the other Low Energy Peripherals, and for

these peripherals, a write operation requires 3 positive edges on the clock of the Low Energy Peripheral

being accessed. Registers requiring synchronization are marked "Asynchronous" in their description

header.

5.3.1.1.1 Delayed synchronization

After writing data to a register which value is to be synchronized into the Low Energy Peripheral using

delayed synchronization, a corresponding busy flag in the <module_name>_SYNCBUSY register (e.g.

LEUART_SYNCBUSY) is set. This flag is set as long as synchronization is in progress and is cleared

upon completion.

Note

Subsequent writes to the same register before the corresponding busy flag is cleared is not

supported. Write before the busy flag is cleared may result in undefined behavior.

In general, the SYNCBUSY register only needs to be observed if there is a risk of multiple

write access to a register (which must be prevented). It is not required to wait until the

relevant flag in the SYNCBUSY register is cleared after writing a register. E.g EM2 can be

entered immediately after writing a register.

See Figure 5.3 (p. 18) for a more detailed overview of the write operation.

Figure 5.3. Write operation to Low Energy Peripherals

Synchronizer 0

Synchronizer 1

Synchronizer n

Write[0:n]

Syncbusy Register 0

Syncbusy Register 1

Syncbusy Register n

Set 0

Set 1

Set n

Freeze

Synchronization Done

Clear 0

Clear 1

Clear n

Core Clock

Low Frequency Clock Low Frequency Clock

Core Clock Domain Low Frequency Clock Domain

5.3.1.1.2 Immediate synchronization

Contrary to the peripherals with delayed synchronization, data written to peripherals with immediate

synchronization, takes effect in the peripheral immediately. They are updated immediately on the

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peripheral write access. If a write is set up close to a peripheral clock edge, the write is delayed to after

the clock edge. This will introduce wait-states on peripheral access. In the worst case, there can be three

wait-state cycles of the HFCORECLK_LE and an additional wait-state equivalent of up to 315 ns.

For peripherals with immediate synchronization, the SYNCBUSY registers are still present and serve two

purposes: (1) commands written to a peripheral with immediate synchronization are not executed before

the first peripheral clock after the write. During this period, the SYNCBUSY flag in the command register

is set, indicating that the command has not yet been executed; (2) to maintain backwards compatibility

with the EFM32G series, SYNCBUSY registers are also present for other registers. These are however,

always 0, indicating that register writes are always safe.

Note

If the application must be compatible with the EFM32G series, all Low Energy Peripherals

should be accessed as if they only had delayed synchronization, i.e. using SYNCBUSY.

5.3.1.2 Reading

When reading from Low Energy Peripherals, the data is synchronized regardless of the originating clock

domain. Registers updated/maintained by the Low Energy Peripheral are read directly from the Low

Energy clock domain. Registers residing in the core clock domain, are read from the core clock domain.

See Figure 5.4 (p. 19) for a more detailed overview of the read operation.

Note

Writing a register and then immediately reading back the value of the register may give the

impression that the write operation is complete. This is not necessarily the case. Please

refer to the SYNCBUSY register for correct status of the write operation to the Low Energy

Peripheral.

Figure 5.4. Read operation from Low Energy Peripherals

Synchronizer 0

Synchronizer 1

Synchronizer n

Freeze

Core Clock

Low Frequency Clock Low Frequency Clock

Core Clock Domain Low Frequency Clock Domain

Low Energy

Peripheral

Main

Function

HW Status Register 0

HW Status Register 1

HW Status Register m

Read

Synchronizer

Read Data

5.3.2 FREEZE register

For Low Energy Peripherals with delayed synchronization there is a <module_name>_FREEZE register

(e.g. RTC_FREEZE), containing a bit named REGFREEZE. If precise control of the synchronization

process is required, this bit may be utilized. When REGFREEZE is set, the synchronization process is

halted, allowing the software to write multiple Low Energy registers before starting the synchronization

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