TI PCM6120-Q1: 2-Channel High-Performance Audio ADC with Advanced Features

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TI-PCM6120-Q1是一款多通道高性能音频ADC，专为音频应用设计，提供了丰富的功能和特性。这款芯片支持两种模拟麦克风输入（2通道）和4通道数字PDM麦克风输入，能够灵活处理多种音频源。其主要特点包括： 1. 高动态范围（DR）：在启用动态范围增强器（DRE）的情况下，能实现高达123分贝的动态范围，而在DRE关闭时也能达到113分贝，确保了出色的信号处理性能。 2. 总体失真加噪声比（THD+N）达到了惊人的-95分贝，显示了极低的非线性失真。 3. ADC支持通道合并模式，当使用2通道并联时，在DRE关闭状态下可达到116分贝的动态范围。 4. 输入电压灵活性：支持差分输入，最大电压范围为2 VRMS全量程，同时也支持单端输入，最大电压为1 VRMS全量程。 5. 可编程通道设置：用户可以调整通道增益，从0分贝到42分贝，步进0.5分贝，以适应不同应用场景；配备数字音量控制，范围从-100分贝到27分贝，并具有0.1分贝的高精度校准能力。 6. 阶段校准功能提供163纳秒的分辨率，确保信号同步的准确性。 7. 内置高精度的麦克风偏置电压生成，支持自定义供应电压，满足不同麦克风的工作需求。 8. 提供低延迟信号处理选项，包括可编程的高通滤波器和双二阶数字滤波器，有助于优化音频质量和减少噪声。 9. 配备自动增益控制器（AGC），能够动态调整输入信号的增益，确保在各种输入条件下都能稳定工作。 10. 嵌入式语音活动检测（VAD）功能，可根据语音活动自动调整处理策略，节省功耗。 11. 通信接口方便，采用I2C控制，便于系统集成和配置。 12. 集成了高性能处理单元，确保实时数据转换和高效音频处理能力。 TI-PCM6120-Q1是一款适合音频采集、处理和系统集成的高级音频ADC解决方案，它结合了高精度、可编程性和低功耗特性，为音频设备设计提供了强大的工具。

7.11 Typical Characteristics (continued)

at T

= 25°C, AVDD = 3.3 V, IOVDD = 3.3 V, f

= 1-kHz sinusoidal signal, f

= 48 kHz, 32-bit audio data, BCLK = 256 ×

, TDM slave mode, PLL on, DRE_LVL = –36 dB, channel gain = 0 dB, and linear phase decimation filter (unless otherwise

noted); all performance measurements are done with a 20-kHz, low-pass filter, and an A-weighted filter

Frequency (Hz)

PSRR (dB)

20 30 4050 70 100 200 300 500 1000 2000 5000 10000 20000

-130

-120

-110

-100

-90

-80

-70

-60

D013

Channel 1

Channel 2

Figure 7-16. Power-Supply Rejection Ratio vs Ripple Frequency

With 100-mV

Amplitude

Frequency (Hz)

Output Amplitude (dBFS)

20 30 4050 70 100 200 300 500 1000 2000 5000 10000 20000

-200

-180

-160

-140

-120

-100

-80

-60

-40

-20

D014

Channel-1 : DRE enabled

Channel-2 : DRE enabled

Figure 7-17. FFT With Idle Input With DRE Enabled

Frequency (Hz)

Output Amplitude (dBFS)

20 30 4050 70 100 200 300 500 1000 2000 5000 10000 20000

-200

-180

-160

-140

-120

-100

-80

-60

-40

-20

D015

Channel-1 : DRE disabled

Channel-2 : DRE disabled

Figure 7-18. FFT With Idle Input With DRE Disabled

Frequency (Hz)

Output Amplitude (dBFS)

20 30 4050 70 100 200 300 500 1000 2000 5000 10000 20000

-200

-180

-160

-140

-120

-100

-80

-60

-40

-20

D016

Channel-1 : DRE enabled

Channel-2 : DRE enabled

Figure 7-19. FFT With a –60-dBr Input With DRE Enabled

Frequency (Hz)

Output Amplitude (dBFS)

20 30 4050 70 100 200 300 500 1000 2000 5000 10000 20000

-200

-180

-160

-140

-120

-100

-80

-60

-40

-20

D017

Channel-1 : DRE disabled

Channel-2 : DRE disabled

Figure 7-20. FFT With a –60-dBr Input With DRE Disabled

Frequency (Hz)

Output Amplitude (dBFS)

20 30 4050 70 100 200 300 500 1000 2000 5000 10000 20000

-200

-180

-160

-140

-120

-100

-80

-60

-40

-20

D018

Channel-1 : DRE disabled

Channel-2 : DRE disabled

Figure 7-21. FFT With a –1-dBr Input With DRE Disabled

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7.11 Typical Characteristics (continued)

at T

= 25°C, AVDD = 3.3 V, IOVDD = 3.3 V, f

= 1-kHz sinusoidal signal, f

= 48 kHz, 32-bit audio data, BCLK = 256 ×

, TDM slave mode, PLL on, DRE_LVL = –36 dB, channel gain = 0 dB, and linear phase decimation filter (unless otherwise

noted); all performance measurements are done with a 20-kHz, low-pass filter, and an A-weighted filter

Frequency (Hz)

CMRR (dB)

20 30 4050 70 100 200 300 500 1000 2000 5000 10000 20000

-130

-120

-110

-100

-90

-80

-70

-60

D019

Channel 1-- DRE Disabled

Channel 2-- DRE Disabled

High CMRR mode

Figure 7-22. Common-Mode Rejection Ratio vs Ripple

Frequency With 100-mV

Amplitude and DRE Disabled

Frequency (Hz)

CMRR (dB)

20 30 4050 70 100 200 300 500 1000 2000 5000 10000 20000

-130

-120

-110

-100

-90

-80

-70

-60

D020

Channel 1 : DRE Enabled

Channel 2 : DRE Enabled

High CMRR mode

Figure 7-23. Common-Mode Rejection Ratio vs Ripple

Frequency With 100-mV

Amplitude and DRE Enabled

Channel Gain (dB)

Input Referred Noise (PV

RMS

)

0 4 8 12 16 20 24 28 32 36 40 44

THD+D021

Channel 1 : DRE Disabled

Channel 2 : DRE Disabled

High CMRR mode

Figure 7-24. Input-Referred Noise vs Channel Gain

Input Amplitude (dB)

THD+N (dBFS)

-130 -115 -100 -85 -70 -55 -40 -25 -10 0

-130

-120

-110

-100

-90

-80

-70

-60

THD+D022

Channel-1 : DRE Enable

Channel-2 : DRE Enable

Differential input with high CMRR mode

Figure 7-25. THD+N vs Input Amplitude With DRE Enabled

Input Amplitude (dB)

THD+N (dBFS)

-130 -115 -100 -85 -70 -55 -40 -25 -10 0

-130

-120

-110

-100

-90

-80

-70

-60

THD+D023

Channel-1 : DRE Disable

Channel-2 : DRE Disable

Differential input with high CMRR mode

Figure 7-26. THD+N vs Input Amplitude With DRE Disabled

Frequency (Hz)

THD+N (dBFS)

20 30 4050 70 100 200 300 500 1000 2000 5000 10000 20000

-130

-120

-110

-100

-90

-80

-70

-60

D024

Channel-1

Channel-2

Differential input with high CMRR mode

Figure 7-27. THD+N vs Input Frequency at –1-dBr Input With

DRE Disabled

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8 Detailed Description

8.1 Overview

The PMC6120-Q1 is a high-performance, low-power, flexible, 2-channel, audio analog-to-digital converter

(ADC) with extensive feature integration. This device is intended for applications in voice-activated

systems, professional microphones, audio conferencing, portable computing, communication, and entertainment

applications. The high dynamic range of the device enables far-field audio recording with high fidelity.

This device integrates a host of features that reduces cost, board space, and power consumption in space-

constrained, battery-powered, consumer, home, and industrial applications.

The PMC6120-Q1 consists of the following blocks:

• 2-channel, multibit, high-performance delta-sigma (ΔΣ) ADC

• Configurable single-ended or differential audio inputs

• Low-noise, programmable microphone bias output

• Dynamic range enhancer (DRE) to support a 123-dB dynamic range

• Automatic gain controller (AGC)

• Programmable decimation filters with a linear-phase filter or a low-latency filter

• Programmable channel gain, volume control, biquad filters for each channel

• Programmable phase and gain calibration with fine resolution for each channel

• Programmable high-pass filter (HPF), and digital channel mixer

• Pulse density modulation (PDM) microphone 4-channel interface with a high-performance decimation filter

• Integrated low-jitter phase-locked loop (PLL) supporting a wide range of system clocks

• Integrated digital and analog voltage regulators to support single-supply operation

Communication to the PMC6120-Q1 for configuring the control registers is supported using an I

C interface. The

device supports a highly flexible audio serial interface [time-division multiplexing (TDM), I

S, or left-justified (LJ)]

to transmit audio data seamlessly in the system across devices.

The PMC6120-Q1 can support multiple devices by sharing the common TDM bus across devices. Moreover, the

device includes a daisy-chain feature as well. These features relax the shared TDM bus timing requirements and

board design complexities when operating multiple devices for applications requiring high audio data bandwidth.

Table 8-1 lists the reference abbreviations used throughout this document to registers that control the device.

Table 8-1. Abbreviations for Register References

REFERENCE ABBREVIATION DESCRIPTION EXAMPLE

Page y, register z, bit k Py_Rz_Dk

Single data bit. The value of a

single bit in a register.

Page 4, register 36, bit 0 = P4_R36_D0

Page y, register z, bits k-m Py_Rz_D[k:m]

Range of data bits. A range of

data bits (inclusive).

Page 4, register 36, bits 3-0 = P4_R36_D[3:0]

Page y, register z Py_Rz

One entire register. All eight

bits in the register as a unit.

Page 4, register 36 = P4_R36

Page y, registers z-n Py_Rz-Rn

Range of registers. A range of

registers in the same page.

Page 4, registers 36, 37, 38 = P4_R36-R38

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The bus protocol TDM, I

S, or left-justified (LJ) format can be selected by using the ASI_FORMAT[1:0]

(P0_R7_D[7:6]) register bits. As shown in Table 8-2 and Table 8-3, these modes are all most significant byte

(MSB)-first, pulse code modulation (PCM) data format, with the output channel data word-length programmable

as 16, 20, 24, or 32 bits by configuring the ASI_WLEN[1:0] (P0_R7_D[5:4]) register bits.

Table 8-2. Audio Serial Interface Format

P0_R7_D[7:6] : ASI_FORMAT[1:0] AUDIO SERIAL INTERFACE FORMAT

00 (default) Time division multiplexing (TDM) mode

01 Inter IC sound (I

S) mode

10 Left-justified (LJ) mode

11 Reserved (do not use this setting)

Table 8-3. Audio Output Channel Data Word-Length

P0_R7_D[5:4] : ASI_WLEN[1:0] AUDIO OUTPUT CHANNEL DATA WORD-LENGTH

00 Output channel data word-length set to 16 bits

01 Output channel data word-length set to 20 bits

10 Output channel data word-length set to 24 bits

11 (default) Output channel data word-length set to 32 bits

The frame sync pin, FSYNC, is used in this audio bus protocol to define the beginning of a frame and has the

same frequency as the output data sample rates. The bit clock pin, BCLK, is used to clock out the digital audio

data across the serial bus. The number of bit-clock cycles in a frame must accommodate multiple device active

output channels with the programmed data word length.

A frame consists of multiple time-division channel slots (up to 64) to allow all output channel audio data

transmissions to complete on the audio bus by a device or multiple PMC6120-Q1 devices sharing the same

audio bus. The device supports up to four output channels that can be configured to place their audio data on

bus slot 0 to slot 63. Table 8-4 lists the output channel slot configuration settings. In I

S and LJ mode, the slots

are divided into two sets, left-channel slots and right-channel slots, as described in the Section 8.3.1.2.2 and

Section 8.3.1.2.3 sections.

Table 8-4. Output Channel Slot Assignment Settings

P0_R11_D[5:0] : CH1_SLOT[5:0] OUTPUT CHANNEL 1 SLOT ASSIGNMENT

00 0000 = 0d (default) Slot 0 for TDM or left slot 0 for I

S, LJ.

00 0001 = 1d Slot 1 for TDM or left slot 1 for I

S, LJ.

… …

01 1111 = 31d Slot 31 for TDM or left slot 31 for I

S, LJ.

10 0000 = 32d Slot 32 for TDM or right slot 0 for I

S, LJ.

… …

11 1110 = 62d Slot 62 for TDM or right slot 30 for I

S, LJ.

11 1111 = 63d Slot 63 for TDM or right slot 31 for I

S, LJ.

Similarly, the slot assignment setting for output channel 2 to channel 8 can be done using the CH2_SLOT

(P0_R12) to CH8_SLOT (P0_R18) registers, respectively.

The slot word length is the same as the output channel data word length set for the device. The output channel

data word length must be set to the same value for all PMC6120-Q1 devices if all devices share the same ASI

bus in a system. The maximum number of slots possible for the ASI bus in a system is limited by the available

bus bandwidth, which depends upon the BCLK frequency, output data sample rate used, and the channel data

word length configured.

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