Micron 3D TLC NAND Flash Memory 技术规格

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"Micron 3D TLC B0KB datasheet提供了关于Micron公司3D TLC NAND闪存芯片的详细规格，涵盖了多种型号如MT29F384G08EBHBB、MT29F768G08EEHBB等。这些芯片支持ONFI 4.0协议和JEDEC NAND闪存互操作性标准，采用三阶单元（TLC）技术，并具有不同的存储容量和性能指标，包括NV-DDR3、NV-DDR2、NV-DDR和异步I/O模式下的读写速度。" Micron的3D TLC NAND闪存技术是一种先进的存储解决方案，它通过在单个晶圆上堆叠多层存储单元来实现高密度存储。在这个B0KB系列中，Micron提供了一系列不同容量的芯片，例如384Gb、768Gb、1T2（1 Terabit）、1H2、3Tb和6Tb，满足不同应用场景的需求。这些芯片采用了Open NAND Flash Interface (ONFI) 4.0规范，这是一个行业标准接口，确保与各种控制器的兼容性和简化系统集成。同时，它们符合JEDEC NAND Flash Interoperability (JESD230B)标准，保证了与其他符合该标准的设备的兼容性。 Micron的3D TLC NAND芯片采用三阶单元存储技术，每个单元可以存储3位数据，相比于传统的SLC（单阶单元）和MLC（多阶单元），TLC能提供更高的存储密度，但可能牺牲一些耐用性和写入速度。在性能方面，芯片提供了不同类型的I/O模式，如NV-DDR3、NV-DDR2和NV-DDR。NV-DDR3模式下，时钟周期为3ns，读写带宽可达667MT/s，提供了高速的数据传输能力。NV-DDR2和NV-DDR模式则分别具有3.75ns和10ns的时钟周期，以及相应的读写带宽。对于不需要高性能的应用，芯片还支持异步I/O模式，其读写带宽为50MT/s，最小的tRC/tWC时间为20ns。此外，芯片的数组性能也值得一提，SNAPREAD操作时间仅为58微秒，这是一种快速的读取技术，提高了数据访问效率。单平面读取和写入操作的性能数据也有助于理解芯片在实际应用中的表现。总而言之，Micron的3D TLC NAND B0KB系列芯片集成了高容量、高速度和标准兼容性，是现代存储系统如固态硬盘、移动设备和嵌入式系统的理想选择。这些特性使得它们在大数据、云计算和物联网等领域有广泛的应用前景。

Table 1: Asynchronous, NV-DDR, NV-DDR2, and NV-DDR3 Signal Definitions (Continued)

Asynchro-

nous Signal

NV-DDR Sig-

nal

NV-DDR2 / NV-

DDR3 Signal

Type Description

RE# W/R# RE#, RE_t Input Read enable and write/read: RE# transfers serial data

from the NAND Flash to the host system when the asynchro-

nous interface is active. When the NV-DDR interface is ac-

tive, W/R# controls the direction of DQx and DQS.

– – RE_c Input Read enable complement: Provides a complementary sig-

nal to the read enable signal optionally used in the NV-DDR2

or NV-DDR3 interface for synchronous reference for data

output.

WE# CLK WE# Input Write enable and clock: WE# transfers commands, ad-

dresses when the asynchronous, NV-DDR2, and NV-DDR3 in-

terfaces are active, and serial data from the host system to

the NAND Flash when the asynchronous interface is active.

When the NV-DDR interface is active, CLK latches command

and address cycles.

WP# WP# WP# Input Write protect: Enables or disables array PROGRAM and

ERASE operations.

R/B# R/B# R/B# Output Ready/busy: An open-drain, active-low output that requires

an external pull-up resistor. This signal indicates target array

activity.

Supply V

: Core power supply

CCQ

Supply V

CCQ

: I/O power supply

Supply V

: The V

signal is an optional external high voltage pow-

er supply to the device. This high voltage power supply may

be used to enhance operations (e.g., improved power effi-

ciency).

Supply V

: Core ground connection

SSQ

Supply V

SSQ

: I/O ground connection

– – V

REFQ

Supply V

REFQ

: Reference voltage used with NV-DDR2 and NV-DDR3

interfaces

ZQ ZQ ZQ – Reference pin for ZQ calibration: This is used on ZQ cali-

bration. The ZQ signal shall be connected to Vss through R

resistor.

NC NC NC – No connect: NCs are not internally connected. They can be

driven or left unconnected.

DNU DNU DNU – Do not use: DNUs must be left unconnected.

RFU RFU RFU – Reserved for future use: RFUs must be left unconnected.

Notes:

1. See Device and Array Organization for detailed signal connections.

2. See sections Bus Operation - Asynchronous Interface, Bus Operation - NV-DDR Interface,

Bus Operations - NV-DDR2 Interface, and Bus Operations - NV-DDR3 Interface for de-

tailed Asynchronous, NV-DDR, NV-DDR2, and NV-DDR3 interface signal descriptions.

Micron Confidential and Proprietary Advance

TLC 384Gb to 6Tb Async/Sync NAND

Asynchronous, NV-DDR, NV-DDR2, NV-DDR3 Signal Descrip-

tions

PDF: 09005aef86697e57

B0KB_Fortis_384Gb_768Gb_1HTb_1Tb_3Tb_6Tb_Sync_NAND_Datasheet Rev. E 7/1/16 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

Release: 7/1/16

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