两层PEC表面的间隙波导PMC封装优化与应用

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本文是一篇研究论文，发表在《IEEE Transactions on Components, Packaging and Manufacturing Technology》第6卷第6期，2016年6月刊上，标题为“两层PEC表面的间隙波导PMC包装”（Gap Waveguide PMC Packaging for Two-Layer PEC Surfaces）。作者为Jing Zhang（学生会员，IEEE）、Xiupu Zhang（资深会员，IEEE）和Dongya Shen（成员，IEEE）。研究焦点集中在对具有不规则形状的双层金属表面构成的理想电导体（Perfect Electric Conductor，PEC）的间隙波导（Gap Waveguide，GW）包装技术进行深入探讨。文章特别关注了GW的阻带设计，这个阻带受上层PEC宽度、引脚尺寸、引脚高度、以及介电基板厚度和介电常数的影响。作者提出了一种针对这种特殊结构的GW包装策略，其目标是优化信号传输性能并减小电磁干扰。论文不仅理论分析了单元格为基础的阻带特性，还展示了如何将这种包装应用到基于 substrate-integrated waveguide (SIW) - microstrip line 的电路结构中，这是双层PEC表面电路设计的典型案例。设计者们构建了一个基于SIW和微带线的切比雪夫带通滤波器，以此作为实验验证手段，特别是针对SIW中存在侧边空气间隙这一特点进行针对性优化。通过实验设计和制造，该滤波器提供了实际操作中的性能数据，验证了提出的GW包装方法的有效性和实用性。这项研究对于改进双层PEC结构的电子设备封装，提升信号处理性能，以及减少电磁兼容性问题具有重要意义，为微电子器件的紧凑化和高密度封装技术开辟了新的可能。整个研究过程展示了理论与实践相结合的研究方法，为未来的高性能集成电路设计提供了有价值的技术参考。

908 IEEE TRANSACTIONS ON COMPONENTS, PACKAGING AND MANUFACTURING TECHNOLOGY, VOL. 6, NO. 6, JUNE 2016

Fig. 3. Change in stopband with top-layer PEC width at three different

substrate heights. (a) Lower and higher cutoff frequencies. (b) Zoomed-in

view of lower cutoff frequencies. A square-shaped pin with a size of 3.0 mm

is used.

pin height is smaller than 2.0 mm, the higher cutoff frequency

even rises immediately as far as the width of the top PEC

surface is larger than zero. This is very different from the

substrate height effect presented in Figs. 2 and 3. The lower

cutoff frequencies, however, are quite different for different

pin heights, but the top PEC surface width impact is negligible

as shown in Fig. 4(b), similar to Figs. 2 and 3 for different

substrate heights.

Further, Fig. 5(a) reveals that a larger air gap height reduces

the higher cutoff frequencies and makes the higher cutoff more

sensitive to the top-layer PEC width. The evidence is that for

an air gap of 2.0 mm, the higher cutoff frequency starts rising

at a narrower top-layer PEC width, compared with the air gap

of 0.5- and 1.0-mm height. This is opposite for the lower cutoff

seen in Fig. 5(b). For example, for a smaller air gap height

of 0.5 mm, a larger drop range of the lower cutoff frequencies

is presented with increased top-layer PEC width. Even so,

the total variation range of the lower cutoff frequencies is still

very small in comparison with that of the higher cutoff.

C. Number of Metal Pin Columns

The study of a GW including two-layer PEC surfaces should

consider different PMC conﬁgurations; thus, in this part,

two more PMC lids of pins are built, which employ six-

and seven-column pins. Moreover, this is also needed for

a large circuit or other purposes where more pins are required.

Fig. 4. Change in stopband with top-layer PEC width at four different pin

heights. (a) Higher cutoff frequencies. (b) Lower cutoff frequencies.

The pins of the built PMC lids have the same dimensions

as given above: pin size of 1.5 mm, pin height of 5.0 mm,

air gap height of 1.0 mm, and cell period of 6.0 mm. The

total width (W) is increased from 30 mm to 36 and 42 mm,

respectively, due to the increased pin columns of six and

seven. The adopted substrate is Rogers RT/Duroid 6002 with

of 2.94 and height of 0.762 mm.

The simulated results for the built lids of pins with different

columns are presented in Fig. 6. It can be seen that the created

higher cutoff frequencies have the same minimum value for

ﬁve-, six-, and seven-column pins. Although the three higher

cutoff curves rise at different top-layer PEC widths, they all

happen when the PEC width extends so big that the substrate

has a width of only one cell period of 6.0 mm. Fig. 6(b) then

shows that the three generated lower cutoff frequencies have

a small decline with the top-layer PEC width. And they all

drop down once the PEC width is larger than zero and arrive

at the minimum value when the top PEC surface width is

equal to the total width (W). But for a particular top-layer PEC

width, such as 21 mm, the PMC lid with more columns of pins

apparently hinders the decline of the lower cutoff frequencies.

D. Substrates With Different Permittivities

The last factor considered in the cell-based analysis of the

two-layer PEC surfaces is the dielectric substrate permittivity,

since the uncovered substrate is exposed to PMC shielding

and thus its permittivity will affect the created stopband [21].

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