3D IC的TSV对准优化设计

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"多层3D IC的TSV对准设计" 在当前的微电子技术领域，随着集成电路（IC）的持续发展，传统的2D IC结构已经无法满足日益增长的性能需求，尤其是面对大规模互连带来的高延迟和功率消耗问题。为了解决这些问题，三维集成电路（3D IC）成为了一个极具潜力的解决方案。3D IC通过垂直堆叠多个芯片并使用贯穿硅通孔（Through-Silicon Via，TSV）来实现芯片间的互连，从而极大地提高了系统性能和能效。 TSV作为3D IC中的关键组成部分，其位置布局对于整个集成电路的可靠性和性能至关重要。不规则的TSV放置可能导致制造过程中的可靠性问题，例如信号完整性、热应力以及机械稳定性等。因此，"多层3D IC的TSV对准设计"这篇研究论文提出了一种TSV对准算法，旨在实现无重叠且接近规则的TSV布局，以减少潜在的可靠性风险。该设计的核心是一个TSV对准算法，该算法可以将初始的不规则TSV布局转换为一个接近规则的布局，确保TSV之间没有重叠。这有助于优化互连路径，降低串扰，提高信号传输速度，并减少功耗。实验基于IBM的基准电路进行了2D到3D的转换，结果显示，这种设计能够成功地实现无重叠且接近规则的TSV布局，从而验证了其有效性和可行性。在3D IC的制造过程中，TSV的对准精度是至关重要的。不准确的对准可能导致TSV与目标连接点的错位，进而影响芯片间的通信质量和整体电路性能。因此，该研究的TSV对准设计对于提升3D IC制造工艺的精确度和可靠性具有重要意义。同时，它也为未来更复杂的3D IC架构提供了基础性技术支持，这些架构可能需要更精细的TSV布局策略以应对更高的互连密度和更复杂的系统集成。此外，TSV的材料选择、尺寸优化、热管理以及封装技术也是3D IC发展中不可忽视的方面。这些因素与TSV对准设计相互关联，共同决定了3D IC的整体性能和使用寿命。因此，未来的研究还需要进一步探索这些方面，以推动3D IC技术的不断发展和完善。

A TSV Alignment Design for Multilayer 3D IC

Wei Zhao, Ligang Hou* , Xiaohong Peng, Jinhui Wang, Jingyan Fu, Yang Yang

VLSI & System Lab, Beijing University of Technology, Beijing 100124, China

* Email: houligang@bjut.edu.cn

Abstract

Through-silicon via (TSV) achieves interconnects of

multiple dies in a 3D IC. Previous researches show that

irregular TSV placement may cause reliability issues in

manufacturing. Therefore, this paper forwards a TSV

alignment design in acquiring an overlap-free

near-regular TSV placement. This design features a TSV

alignment algorithm which aligns an irregular TSV

placement into a near-regular one. Experiments are

conducted on 2D-3D transformation of IBM benchmark

circuits. Results show that this design successfully

realizes a near-regular overlap-free TSV placement.

1. Introduction

Three Dimensional ICs (3D ICs) are one of the most

promising technologies in solving problems of 2D ICs,

such as high delays and power consumptions brought by

large scale interconnects. A 3D IC consists of multiple

dies where gates are placed. These dies are stacked

vertically and connected through vertical interconnects

called through-silicon vias (TSVs).

Depending on when the TSVs are fabricated, there exist

two major types of TSV: via-first TSVs and via-last

TSVs [1]. Via-first TSVs have typically smaller

diameters (1-5μm) while via-last TSVs have typically

larger diameters (5-20μm) [2]. TSVs are usually etched

or drilled through substrates by certain techniques and

filled with conductive materials like copper [1].

Although TSVs achieve connections across dies, they

also have negative effects on 3D IC design. For instance,

inserting a great amount of TSVs occupies large silicon

area, which can cause serious area overhead. In addition,

TSVs are connected with gates or other TSVs through

metal layers, so TSVs can also consume enormous

routing resources. Those disadvantages of TSVs

mentioned above are mainly caused by inappropriate

number or position of TSVs [3]. Therefore, new EDA

tools are required for better TSV placement.

As for 3D IC manufacturing, TSVs cause significant

thermomechanical stress that may seriously affect

performance and reliability of circuits [8]. As shown in

reference [8], designs with irregular TSV placement

show worse maximum von Mises stress than those with

the regular TSV placement. In reference [9], irregular

TSV placement suffers from higher energy release rate

(ERR) and larger ERR variation compared with regular

TSV placement.

Many works targeted on 3D IC placement have gained

valuable achievements. In [4], a force directed approach

has been used to move cells in three dimensions for the

reduction of cell overlap and temperature. A

folding/stacking approach is proposed in [5] to transform

2D placement results into 3D. After the transformation, a

graph-based layer assignment method can be used to

reduce the number of TSVs and temperature.

Reference [6] proposes a multilevel non-linear

programming based 3D placement approach that

minimizes a weighted sum of total wirelength and the

number of TSVs. And a density penalty function is used

to remove overlap. In [3], two TSV positioning

algorithms are proposed for optimizing total wirelength.

A TSV based wirelength calculation algorithm is used to

gain the results for comparing those two TSV

positioning algorithms.

Reference [4] does not consider the impact of TSV in

any stage. Although reference [5] and [6] consider the

number of TSVs, they do not take TSV area into account.

Reference [3] considers the position of TSVs, but it does

not consider TSV area either. And all the algorithms in [3]

are applied only in two layer 3D ICs for the experiment.

None of these references achieve a regular overlap-free

TSV placement. Therefore, a TSV alignment process is

needed to acquire a regular overlap-free TSV placement

for manufacturing and better reliability.

In this paper, a near-regular overlap-free TSV alignment

design for multilayer 3D IC is proposed, which the

position of TSVs and TSV area are both considered. The

contributions of our work are listed as following:

1) A TSV alignment flow featured with a TSV

alignment algorithm is proposed, which can be applied

after 2D-3D partitioning.

2) An approach is proposed to remove overlap, while

TSVs are considered as standard cells and placed in rows

of standard cells.

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