Si5341/40：低噪声10路任意频率时钟发生器

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本文档是Silicon Laboratories发布的Si5341/40低抖动、多输出、任意频率、任意输出时钟发生器的数据手册。该器件是一款高度灵活的时钟解决方案，适用于对低抖动性能有严格要求的系统，如通信设备、数据中心和测试设备。主要特性包括： 1. **多输出能力**：Si5341/40可以同时生成多达10个独立的输出时钟，满足复杂系统中多个时钟源的需求。 2. **超低抖动**：通过采用MultiSynth™技术，该时钟发生器在典型条件下实现小于100飞秒（fs）的相位随机噪声，确保了时钟信号的极高稳定性和准确度。 3. **任意频率与输出选择**：器件支持任何频率的合成，并且可以根据应用需求选择不同的输出接口类型，如LVDS、LVPECL、CML、LVCMOS、HCSL或可编程电压。 4. **宽频输入范围**：支持外部晶体振荡器频率在25到54MHz，差分时钟输入范围从10MHz到750MHz，LVCMOS输入则为10MHz到250MHz。 5. **宽频输出范围**：输出频率可覆盖从100Hz到712.5MHz（差分），以及100Hz到250MHz（LVCMOS），并且具有20ps的典型输出-输出偏移。 6. **可调延时与零延时模式**：允许用户根据需要调整输出时钟之间的延迟，并提供选项启用零延时模式，以优化时序性能。 7. **动态频率变化下低级联扰**：在输出频率实时改变时，能有效减少时钟间的突发噪声干扰，确保系统稳定性。 8. **精密频率控制**：内部的数字频率合成器具备低至0.001ppb（十亿分之一）的频率步进，确保精确的频率精度。 9. **电源管理**：支持独立的输出时钟供电，如3.3V、2.5V或1.8V，集成电源滤波和调节功能。 10. **状态监测**：内置监视功能，如Loss of Signal (LOS)和Loss of Lock (LOL)，有助于故障诊断。 11. **串行接口**：提供了I2C或SPI接口（3线或4线），便于设备配置和控制。 12. **非易失性存储器**：用户可编程的两组非易失性只读存储器（OTP），方便固件升级和配置设置的长期保存。 Si5341/40是一款高度可定制的时钟发生器，特别适合对低抖动和高灵活性要求严苛的现代电子系统，如无线通信、数据处理和自动化设备中的精密定时任务。

Si5341/40

10 Rev. 1.0

Common Mode Voltage

Normal Mode or Low Power Modes

DDO

= 3.3 V LVDS 1.10 1.25 1.35 V

LVPECL 1.90 2.05 2.15

DDO

= 2.5 V LVPECL

LVDS

1.15 1.25 1.35

DDO

= 1.8 V Sub-LVDS 0.87 0.93 1.0

Rise and Fall Times

(20% to 80%)

Normal Mode — 170 240 ps

Low Power Mode — 300 430

Differential Output Impedance

Normal Mode — 100 — 

Low Power Mode — 650 — 

Power Supply Noise Rejection

PSRR

Normal Mode

10 kHz sinusoidal noise — –93 — dBc

100 kHz sinusoidal noise — –93 —

500 kHz sinusoidal noise — –84 —

1 MHz sinusoidal noise — –79 —

Low Power Mode

10 kHz sinusoidal noise — –98 — dBc

100 kHz sinusoidal noise — –95 —

500 kHz sinusoidal noise — –84 —

1 MHz sinusoidal noise — –76 —

Table 5. Differential Clock Output Specifications (Continued)

= 1.8 V ±5%, V

DDA

=3.3V ±5%, V

DDO

= 1.8 V ±5%, 2.5 V ±5%, or 3.3 V ±5%, T

= –40 to 85 °C)

Parameter Symbol Test Condition Min Typ Max Units

Notes:

1. The typical normal mode (or low power mode) LVDS maximum is 100 mV (or 80 mV) higher than the TIA/EIA-644

maximum. For normal and low-power modes, the amplitudes are programmable through register settings and can be

stored in NVM. Each output driver can be programmed independently. See Appendix A of the Si5341/40 Reference

Manual.

2. Driver output impedance depends on selected output mode (Normal, Low Power).

3. Measured for 156.25 MHz carrier frequency. Sinewave noise added to VDDO (1.8 V = 50 mVpp, 2.5 V/

3.3 V = 100 mVpp) and noise spur amplitude measured.

4. Measured across two adjacent outputs, both in LVDS mode, with the victim running at 155.52 MHz and the aggressor

at 156.25 MHz. Refer to application note, “AN862: Optimizing Si534x Jitter Performance in Next Generation Internet

Infrastructure Systems”, guidance on crosstalk minimization.

5. For other amplitudes see Appendix A of the Si5341/40 Reference Manual.

6. See Note 4, but in this case the measurement is across two output clocks that have a single clock between them.

7. Same as Note 4, but the Si5340 has less crosstalk due to the spacing of adjacent outputs.

OUTx

Vpp_se

Vpp_diff = 2*Vpp_se

Vcm

Si5341/40

Rev. 1.0 11

Output-Output Crosstalk XTALK Si5341

Note

—–75— dBc

Si5341

Note

—–85— dBc

Si5340

Note

—–85— dBc

Table 6. Output Status Pin Specifications

=1.8V ±5%, V

DDA

=3.3V ±5%, V

DDS

= 3.3 V ±5%, 1.8 V ±5%, T

= –40 to 85 °C)

Parameter Symbol Test Condition Min Typ Max Units

Si5341 Status Output Pins (LOL

, INTR), SDA/SDIO

, SDO

Output Voltage V

= –2 mA V

DDIO

x 0.75 — — V

= 2 mA — — V

DDIO

x 0.15 V

Si5340 Status Output Pins (INTR), LOL, LOS_XAXB, SDA/SDIO

, SDO

Output Voltage V

= –2 mA V

DDIO

x 0.75 — — V

= 2 mA — — V

DDIO

x 0.15 V

Notes:

1. V

DDIO

is determined by the IO_VDD_SEL bit. It is selectable as V

DDA

or V

. Refer to the Reference Manual for more

details on register settings.

2. The V

specification does not apply to the open-drain SDA/SDIO output when the serial interface is in I2C mode or is

unused with I2C_SEL pulled high. V

remains valid in all cases.

Table 5. Differential Clock Output Specifications (Continued)

= 1.8 V ±5%, V

DDA

=3.3V ±5%, V

DDO

= 1.8 V ±5%, 2.5 V ±5%, or 3.3 V ±5%, T

= –40 to 85 °C)

Parameter Symbol Test Condition Min Typ Max Units

Notes:

1. The typical normal mode (or low power mode) LVDS maximum is 100 mV (or 80 mV) higher than the TIA/EIA-644

maximum. For normal and low-power modes, the amplitudes are programmable through register settings and can be

stored in NVM. Each output driver can be programmed independently. See Appendix A of the Si5341/40 Reference

Manual.

2. Driver output impedance depends on selected output mode (Normal, Low Power).

3. Measured for 156.25 MHz carrier frequency. Sinewave noise added to VDDO (1.8 V = 50 mVpp, 2.5 V/

3.3 V = 100 mVpp) and noise spur amplitude measured.

4. Measured across two adjacent outputs, both in LVDS mode, with the victim running at 155.52 MHz and the aggressor

at 156.25 MHz. Refer to application note, “AN862: Optimizing Si534x Jitter Performance in Next Generation Internet

Infrastructure Systems”, guidance on crosstalk minimization.

5. For other amplitudes see Appendix A of the Si5341/40 Reference Manual.

6. See Note 4, but in this case the measurement is across two output clocks that have a single clock between them.

7. Same as Note 4, but the Si5340 has less crosstalk due to the spacing of adjacent outputs.

OUTx

Vpp_se

Vpp_diff = 2*Vpp_se

Vcm

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