现代VLSI系统中的时钟系统设计

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"《Clocking in Modern VLSI Systems》由Thucydides Xanthopoulos编辑，探讨了现代VLSI系统中的时钟设计问题。书中涵盖了时钟设计的历史里程碑，如PLL集成、GHz竞赛的崛起、延迟锁定技术、利用电感进行振荡和分布、可变频率（和电压）技术以及通过鲁棒性提高频率或降低电源的方法。此外，还概述了书中的主要内容，包括现代时钟分布系统的定义、设计要求、拓扑结构、微处理器时钟分布以及针对测试和制造的时钟设计策略。" 《Clocking in Modern VLSI Systems》一书深入介绍了时钟在微电子领域的重要性。时钟设计是集成电路设计中的关键部分，因为它直接影响到系统的性能和能效。作者首先提出了时钟设计问题，强调了从早期的简单时钟系统发展到如今复杂、高速的VLSI系统过程中所遇到的挑战。历史上的几个关键里程碑包括：集成PLL（锁相环路）使得时钟同步成为可能，标志着微处理器时钟设计的进步；随着GHz级别的频率竞赛，时钟分布成为了设计的核心问题；延迟锁定技术的出现解决了时钟信号的精确同步；利用电感元件在振荡和分布中发挥作用，提高了时钟效率；可变频率和电压的设计允许系统根据需求动态调整，增强了灵活性；通过提高系统鲁棒性来增加频率或降低电源电压，以应对更高的性能需求。书中详细讨论了现代时钟分布系统，包括定义、设计需求和各种时钟属性。例如，设置和保持定时约束是确保数据正确传输的关键，而时钟的静态和动态不确定性会影响系统稳定性。分布延迟必须被严格控制以确保整个系统的一致性。此外，时钟的占空比也至关重要，因为它影响到数字电路的工作效率。时钟分布的功率消耗是另一个设计考虑因素，尤其是在追求低功耗的现代IC设计中。时钟分布的拓扑结构多种多样，包括无约束树、平衡树、中央脊椎、匹配分支脊椎、网格布局以及混合分布等。每种结构都有其独特的优点和适用场景。微处理器的时钟分布则更为复杂，需要适应多核架构和大规模逻辑电路的需求。为了测试和制造过程，时钟设计需要额外的补偿策略，如全局和局部时钟补偿，以确保在不同条件下的可靠性和一致性。全局时钟补偿架构关注于整个系统层面的时钟同步，而局部时钟补偿则更专注于芯片内部的局部区域。此外，时钟分布电路的组成元素，如时钟占空比控制和电源管理，对系统的整体性能和效率产生直接影响。最后，书中还介绍了时钟DFX（设计-for-test/exchange）技术，如光学探测和内置自测技术，这些技术有助于提升测试和故障诊断的效率。《Clocking in Modern VLSI Systems》提供了全面的时钟设计理论与实践知识，对于理解现代VLSI系统中的时钟技术及其在ASIC（应用专用集成电路）中的应用具有重要价值。

XVI List of Figures

2.28 Asymmetric clock tree distribution with multiple regions .............. 31

2.29 Multilevel symmetric H-Tree distribution ........................... 32

2.30 Delay characteristics of a multilevel tree-grid distribution ............. 32

2.31 Centralized clock drivers with grids on three generations

of the Alpha

 microprocessor ................................... 33

2.32 Recombinant clock tiles on a 90nm processor ....................... 33

2.33 Pentium

 4 processor clock distribution using centralized spines with

delay matched ﬁnal branches . .................................... 34

2.34 Clock distribution of a low power IA processor consisting of binary

trees embedded in the centralized spines. . . . . . ...................... 34

2.35 Hybrid spine-grid clock distribution in a dual-core processor .......... 35

2.36 Local clock distribution of the hybrid spine-grid clock distribution ...... 36

2.37 Dual-zone deskew architecture.................................... 37

2.38 Deskew delay line structure ...................................... 38

2.39 Deskew zones in the itanium

 processor ........................... 38

2.40 Clocking architecture of the ﬁrst itanium

 processor ................ 39

2.41 Deskew controller and deskew buffer design ........................ 40

2.42 Pentium

 4 processor deskew architecture ......................... 40

2.43 Before and after skew proﬁle of the Pentium

 4 processor ............ 41

2.44 Hierarchical deskew architecture of a dual-core processor ............. 41

2.45 H-tree deskew topology ......................................... 42

2.46 Mesh deskew topology .......................................... 43

2.47 Local clock compensation........................................ 44

2.48 F

max

shift caused by duty cycle distortion in a phase-path dominated

design ........................................................ 45

2.49 Duty cycle distortion due to asymmetric edge propagation between a

buffer-based clock distribution and an inverter-based clock distribution . . 46

2.50 Duty cycle corrector ............................................ 46

2.51 Duty cycle corrector circuits...................................... 47

2.52 Clock buffer design with power-supply ﬁlters ....................... 47

2.53 On-die clock tree ﬁlter circuit..................................... 48

2.54 Back-side optical probing technique (a) ............................ 49

2.55 Back-side optical probing technique (b) ............................ 49

2.56 Skew and jitter measurement circuit ............................... 50

2.57 Sampled delay pattern of the skew and jitter measurement circuit ....... 50

2.58 Vernier delay line ............................................... 51

2.59 Vernier delay line timing example ................................. 51

2.60 On-die-clock shrink architecture .................................. 52

2.61 ODCS clock waveform .......................................... 53

2.62 ODCS capabilities .............................................. 54

2.63 Globally asynchronous and locally synchronous architecture........... 55

2.64 Multidomain clocking in a dual-core processor ...................... 56

2.65 Clock distribution of an 80-tile processor design ..................... 57

3.1 Latency (d −q time) vs. data arrival time for two hypothetical CSE designs 69

List of Figures XVII

3.2 Power vs. input data switching factor for two hypothetical

CSEdesigns................................................... 70

3.3 Basic scan design. Scan data ﬂow is indicated by the dotted lines ....... 71

3.4 Master–slave latch .............................................. 72

3.5 MSL hold time vs. total MSL latency as the cycle boundary overlap of

dclkandlclkisvaried........................................... 73

3.6 Scannable MSL ................................................ 74

3.7 Sample set of clock waveforms for scan shifting and for functional

operation, for the MSL of Fig.3.6 ................................. 75

3.8 MSL with scan MUX in feedback path ............................. 75

3.9 Basic two-phase level-sensitive latch scheme, with sample local clock

waveforms .................................................... 76

3.10 Scannable level-sensitive latch .................................... 77

3.11 Simple non-scan pulsed-clock latch................................ 78

3.12 Scannable pulsed-clock latch with built-in MSL-mode fallback ........ 79

3.13 Sense-Amp ﬂip-ﬂop ............................................ 81

3.14 Improved scannable sense-Amp ﬂip-ﬂop, with asynchronous reset ...... 82

3.15 Hybrid latch ﬂip-ﬂop ............................................ 82

3.16 Semi-dynamic ﬂip-ﬂop with embedded dynamic logic ................ 84

3.17 Scannable semi-dynamic ﬂip-ﬂop ................................. 85

3.18 Scan test conﬁgurations.......................................... 86

3.19 Sample clock waveforms for AC test using MSL from Fig.3.6 ......... 87

3.20 Programmable delay line deﬁning the trailing edge

of a local clock pulse ............................................ 90

3.21 DICE latch topology ............................................ 92

3.22 Scannable pulsed-clock DICE latch................................ 93

3.23 Razor master–slave latch......................................... 94

3.24 Transition detection scheme ...................................... 95

4.1 Common 2-turn spiral inductor shapes ............................. 107

4.2 Spiral inductor narrowband lumped model .......................... 108

4.3 Transmission line lumped model .................................. 111

4.4 Finite-length transmission line with termination ..................... 112

4.5 Microstrip transmission line with and without ground shield ........... 113

4.6 Coplanar transmission line with and without ground shield ............ 114

4.7 U-shaped coplanar waveguide .................................... 115

4.8 Coplanar differential transmission line without ground shield .......... 115

4.9 Differential LC VCO circuit topologies ............................ 116

4.10 Quadrature LC VCO block diagram

............................... 118

4.11 Parallel-coupled quadrature LC VCOs ............................. 119

4.12 Series-coupled quadrature LC VCOs............................... 120

4.13 Parallel-coupled quadrature LC VCO with 90

◦

phase shift in the

coupling phase . . ............................................... 120

4.14 Distributed oscillator ............................................ 121

4.15 Circular distributed oscillator ..................................... 122

4.16 Circular distributed oscillator with clock direction control ............. 123

XVIII List of Figures

4.17 Rotary traveling-wave arrays ..................................... 124

4.18 Standing wave oscillator ......................................... 125

4.19 Coupled standing wave oscillators used for clock

distributionnetwork............................................. 126

4.20 (a) Standing-wave oscillator with inductive loads and (b) Multiple

oscillators magnetically coupled . . . . . ............................. 127

4.21 Circular standing wave oscillator .................................. 128

4.22 Global clock distribution with resonant load ........................ 129

4.23 Lumped circuit model of the clock sector ........................... 129

4.24 Distributed differential global clock network ........................ 130

5.1 Jitter deﬁnitions ................................................ 140

5.2 Phase noise .................................................... 142

5.3 Phase noise decomposition into carrier and L(f) ..................... 143

5.4 PLL block diagram with noise sources included ..................... 144

5.5 VCO noise modeling ............................................ 145

5.6 Tri-state phase-frequency detector (PFD) ........................... 147

5.7 Modiﬁed tri-state phase-frequency detector (PFD) ................... 148

5.8 Charge-pump architecture ........................................ 149

5.9 Charge-pump operation .......................................... 149

5.10 Typical charge-pump PLL passive RC ﬁlter ......................... 150

5.11 PLL noise analysis model proposed in [1] .......................... 153

5.12 PLL noise analysis model proposed in [1] .......................... 154

5.13 Reference clock phase noise to jitter modeling ...................... 157

5.14 Phase to period and C2C jitter difference functions ................... 158

5.15 Reference clock to phase jitter model .............................. 159

5.16 Reference clock to period jitter model.............................. 160

5.17 Reference clock to C2C jitter model ............................... 161

5.18 Reference clock jitter to period jitter model ......................... 162

5.19 Number of

in peak-to-peak calculation for normal distribution ....... 163

5.20 Example transfer functions for period jitter calculation................ 164

5.21 Example reference clock

re f

and ﬁltered

re f

................... 165

5.22 Example transfer functions for period jitter calculation with

added pole. . ................................................... 166

5.23 Example reference clock

nref

and ﬁltered

nref

with added pole ...... 167

5.24 PLL phase noise spectrum showing reference spurs .................. 168

5.25 Deterministic jitter histogram due to reference spurs.................. 169

5.26 Duty cycle distortion ............................................ 170

5.27 Random data signal ﬁltering by a channel .......................... 171

5.28 Eye diagram of ﬁltered data signal................................. 172

5.29 Eye diagram ................................................... 173

5.30 Serial link with separate TX and RX reference clocks ................ 175

5.31 Serial link with common reference clock ........................... 176

5.32 Serial link model with common reference clock and skew ............. 176

5.33 Cancelation of reference clock noise in common clock architecture 1 ... 177

5.34 Cancellation of reference clock noise in common clock architecture 2 ... 178

List of Figures XIX

6.1 Generalized DLL block diagram .................................. 184

6.2 Phase detector transfer function ................................... 185

6.3 Digitally controlled delay line transfer function ...................... 185

6.4 DLL applications ............................................... 186

6.5 Symmetric phase detector out of asymmetric ﬂops ................... 188

6.6 Bang–bang phase detector ....................................... 189

6.7 CMOS inverter voltage transfer function ........................... 193

6.8 CMOS inverter voltage transfer function parametrization .............. 193

6.9 Metastable state in CMOS cross-coupled inverters ................... 194

6.10 Voltage in metastable state ....................................... 194

6.11 Small signal model of cross-coupled inverters ....................... 195

6.12 Valid node voltage region for Eq. (6.17)............................ 197

6.13 Exponential trajectory towards a stable state ........................ 198

6.14 Determining the probability of entering metastability ................. 200

6.15 Determining MTBF with a spice simulation ......................... 202

6.16 NAND-based registered-controlled 4-stage delay line ................. 204

6.17 NAND-based telescopic 4-stage delay line .......................... 205

6.18 Inverter-based logarithmic 4-stage delay line ........................ 205

6.19 Inverter-based differential 4-stage delay line ........................ 206

6.20 Inverter-based conditional-output 4-stage delay line .................. 206

6.21 DCDL spurious output transition .................................. 208

6.22 Duplicating DCDLs for glitch suppression .......................... 209

6.23 Dual output DCDL for glitch suppression........................... 209

6.24 RC-based ﬁne DCDL stages ...................................... 210

6.25 Fine DCDL based on delay differences ............................. 211

6.26 Full swing phase interpolator (log

n-bit control) ..................... 213

6.27 Phase interpolator equivalent circuits .............................. 214

6.28 Phase interpolator normalized voltage output for

t = 0.5,1, 2 ......... 215

6.29 Phase interpolator transfer function for varying

t ................... 216

6.30 DLL control options ............................................ 217

6.31 DLL FSM example for initial condition ﬂexibility ................... 218

6.32 Doubling DLL dynamic range using conditional inversion............. 220

6.33 Analog DLL frequency domain model ............................. 221

6.34 DLL limit cycles as a function of N

............................... 225

6.35 DLL loop stabilization using N

................................. 226

6.36 DLL phase error tracking of SS clock as a function of N

............ 227

6.37 DLL lock acquisition proﬁles ..................................... 228

6.38 Jitter as a function of supply noise frequency and insertion delay ....... 234

6.39 Jitter as a function of insertion delay and supply noise frequency (2D)... 235

6.40 Duty cycle correction in a DLL environment ........................ 237

6.41 Multiperiod DCDL locking for high output frequency

clock multiplication . . . . . ........................................ 238

6.42 Dual DLL architecture for virtually inﬁnite phase capture range ........ 239

6.43 DLL-based clock-data recovery loop ............................... 241

XX List of Figures

7.1 (a) Standard master–slave ﬂip-ﬂop. (b) Creation of a time-borrowing

ﬂip-ﬂopbyinsertingtransparencywindowinverters.................. 247

7.2 NTB and TB N-cycle interconnects ................................ 248

7.3 Timing for a 2-cycle TB interconnect and PDF of stage-delay mismatch

fordeterminingoptimaltransparencywindow....................... 249

7.4 Active and average energies per cycle vs. mean F

MAX

change from NTB

to TB N-cycle interconnect . . . .................................... 250

7.5 Maximum mean F

MAX

gain from NTB to TB N-cycle

interconnect vs. N . . . . . . ........................................ 251

7.6 Clock distribution topology for a 0.18

m, IA-64 microprocessor ...... 253

7.7 Deskew buffer (DSK) architecture and DSK variable delay circuit ...... 254

7.8 Experimental skew measurements ................................. 254

7.9 Clock system architecture for the 90 nm Itanium



processor(Montecito)........................................... 255

7.10 SLCB architecture and RAD SLCB/comparator connections ........... 256

7.11 Dynamic frequency divider (DFD) and phase compensator state

machine (PCSM) block diagram . . . . . ............................. 257

7.12 Regional voltage detector (RVD) details ............................ 257

7.13 Oscilloscope trace of clock system VFM response to 150 mV droop at

2.27GHz,1.2V................................................ 258

7.14 Measured variable-frequency mode (VFM) (%) Frequency increase

over ﬁxed-frequency mode for multiple test cases . . .................. 258

7.15 Overview of 90 nm TCP/IP Processor test chip with dynamic voltage,

frequency, and body bias . ........................................ 259

7.16 Details of dynamic adaptation method ............................. 260

7.17 Dynamic clocking system details .................................. 260

7.18 Measured dynamic frequency response to a voltage droop ............. 261

7.19 Razor error-detection ﬂip-ﬂop .................................... 263

7.20 Error-detection sequential circuits ................................. 264

7.21 Timing diagram for the transition-detection with time-borrowing

(TDTB) technique . . . . . . ........................................ 265

7.22 Details of the Razor-II sequential design ........................... 265

7.23 Timing diagram for the Razor-II design ............................ 266

7.24 Instruction-replay error-recovery design for one error-detection

sequential (EDS) ............................................... 267

7.25 Details of the test chip clock generation ............................ 268

7.26 Overview of 0.13

m, 64-bit, 7-stage alpha processor design

incorporating Razor-II error-detection sequentials

andinstructionreplay ........................................... 269

7.27 Measured Razor-II energy consumption and distribution

of energy savings ............................................... 269

7.28 Measured energy per instruction and error rate

for the Razor-II processor . . . . .................................... 270

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