Marvell 88E6085：10口Fast Ethernet交换芯片 datasheet
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更新于2024-07-16
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收藏 2.35MB PDF 举报 "88E6085.pdf是Marvell公司的一款8口Fast Ethernet交换芯片的datasheet，主要介绍了其在SOHO路由器和网关应用中的独特设计和高性能特性。该芯片集成了10个10BASE-T/100BASE-TX收发器（PHYs）和两个MII接口，支持最佳服务质量（QoS）和实际环境下的高性能。它具备真正的即插即用功能，如自动交叉、自动协商和自动极性校正。此外，还包含了防止桥接环路的功能。88E6085含有10个独立的802.3媒体访问控制器（MACs），一个高速非阻塞的四类流量QoS交换矩阵，以及独特的Marvell动态队列限制架构。设备支持基于端口、802.1p、IPv4服务类型（TOS）、区分服务（Diff-Serv）、IPv6流量类别、802.1Q VLAN ID、目的MAC地址或源MAC地址的四类流量队列。"
该芯片提供高达2K活动节点的高性能地址查找引擎和1M比特帧缓冲内存。为了在临时交通拥塞时实现零包丢失，它包括了背压和基于暂停帧的流量控制策略。MAC单元完全符合IEEE 802.3标准。两个MII接口支持与集成MAC的管理或路由器CPU的直接连接，支持MII-PHY模式或MII-MAC模式。这些接口结合IEEE 802.1D生成树协议、802.1w快速生成树、802.1s多VLAN生成树、可编程的端口VLAN配置、802.1Q和端口状态，支持全管理交换机和真正隔离的WAN与LAN防火墙应用。
88E6085支持64个802.1Q VLAN ID，可在每个端口基础上启用，并提供三层802.1Q安全功能，具有错误帧捕获和日志记录。它还支持多个地址数据库，允许在不修改MAC地址的情况下进行数据包路由，确保WAN和LAN数据库的完全隔离。
88E6085的集成PHY采用Marvell的尖端混合信号处理技术，实现自适应均衡和时钟数据恢复的数字实现。特殊电源管理技术用于降低功耗并支持高端口计数集成。无论是PHY单元还是MAC单元，均全面符合IEEE 802.3、IEEE 802.3u和IEEE 802.3x标准。文档状态为“预发布”，表示内容可能随产品开发而变化，需联系Marvell的现场应用工程师获取更多信息。
168o08yy5q-ffjdne1h * Itibia Technologies Co Ltd
MARVELL CONFIDENTIAL, UNDER NDA# 12109049
168o08yy5q-ffjdne1h * Itibia Technologies Co Ltd
MARVELL CONFIDENTIAL, UNDER NDA# 12109049
168o08yy5q-ffjdne1h * Itibia Technologies Co Ltd * UNDER NDA# 12109049
MARVELL CONFIDENTIAL - UNAUTHORIZED DISTRIBUTION OR USE STRICTLY PROHIBITED
Doc. No. MV-S104212-00 Rev. B
CONFIDENTIAL
Copyright © 2008 Marvell
Page 16 Document Classification: Proprietary Information January 30, 2008, Advance
Link Street
®
88E6085
10 Port 10/100 Ethernet Switch with 8 Transceivers, QoS, and 802.1Q
Figure 41: Format of a VTU Entry...................................................................................................................... 150
Figure 42: Format of an STU Entry .................................................................................................................... 155
Figure 43: Remote Management DSA Tag Request Format ............................................................................. 160
Figure 44: Remote Management DSA Tag Response Format .......................................................................... 162
Figure 45: Remote Management Generic Layer 3 Request Format .................................................................. 164
Figure 46: Remote Management Generic Layer 3 Response Format ............................................................... 165
Figure 47: Remote Management ATU Dump Response Format ....................................................................... 167
Figure 48: Remote Management MIB Dump Response Format........................................................................ 169
Figure 49: Remote Management Register Read/Write Response Format ........................................................ 171
Figure 50: Remote Management Error Response Format................................................................................. 172
Figure 51: Device Transmit Block Diagram........................................................................................................ 173
Figure 52: Device Receive Block Diagram......................................................................................................... 174
Figure 53: Line Loopback Data Path.................................................................................................................. 187
Figure 54: Possible Solutions for Case One ...................................................................................................... 191
Figure 55: Possible Solutions for Case Two ...................................................................................................... 192
Figure 56: Typical MDC/MDIO Read Operation................................................................................................. 193
Figure 57: Typical MDC/MDIO Write Operation................................................................................................. 193
Figure 58: Device Register Map......................................................................................................................... 203
Figure 59: Per Port Register Bit Map ................................................................................................................. 204
Figure 60: Global Register Bit Map .................................................................................................................... 239
Figure 61: Global 2 Register bit Map (Device Addr 0x1C) ................................................................................. 269
Figure 62: PIRL Register bit Map (from Global 2 offsets 0x09 & 0x0A).............................................................290
Figure 63: Extended EEPROM Format...............................................................................................
............... 301
Figure 64: Cable Fault Distance Trend Line ...................................................................................................... 330
Figure 65: Reset and Configuration Timing ....................................................................................................... 338
Figure 66: Oscillator Clock Timing ..................................................................................................................... 339
Figure 67: MII Clock Timing ............................................................................................................................... 340
Figure 68: MII Receive Timing ........................................................................................................................... 342
Figure 69: MII Transmit Timing .......................................................................................................................... 344
Figure 70: SMI Clock Timing (CPU Set) ............................................................................................................ 345
Figure 71: SMI Data Timing ............................................................................................................................... 346
Figure 72: SMI Timing Input (PHY Mode).......................................................................................................... 347
Figure 73: SMI Timing Output (PHY Mode) ....................................................................................................... 347
Figure 74: 2-Wire Input Timing........................................................................................................................... 348
Figure 75: 2-Wire Output Timing........................................................................................................................ 349
Figure 76: 4-Wire EEPROM Timing ................................................................................................................... 350
Figure 77: 176-pin TQFP EPAD Package Mechanical Drawings ...................................................................... 352
Figure 78: Sample Part Number ........................................................................................................................ 354
Figure 79: 88E6085 176-pin TQFP Commercial RoHS 6/6 Compliant Package Marking and Pin 1 Location .. 355
Figure 80: 88E6085 176-pin TQFP Industrial RoHS 6/6 Compliant Package Marking and Pin 1 Location ....... 355
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