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PowerPC e5500核心参考手册更新:2015年版本
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更新于2024-07-17
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"《PowerPC e5500核心用户手册更新》"
本资源是一份针对PowerPC嵌入式开发的专业文档,名为"e5500RM.pdf",由Freescale Semiconductor发布,最后一次更新日期为2015年6月24日。这份手册是e5500处理器的核心参考手册的第四版修订版,旨在提供对原有内容的更新和修正。
更新内容主要包括对9.11.6节(原页码9-78)的调整。在表格9-47的"性能监控事件选择"部分,原先的描述"LRU"被更正为"LSU",这可能涉及到处理器性能指标或系统资源管理的细微改动。这种类型的变更对于开发者来说非常重要,因为正确理解和利用这些性能监控事件可以帮助优化代码并提高系统效率。
此外,还有一份更新于2015年1月22日的文档,同样提供了对e5500 Core Reference Manual Rev.4的补充,强调了提供更新项目在参考手册中的章节号和页面号以便查找。这意味着手册可能会包含更多关于硬件特性、指令集、异常处理、内存管理等多方面的细节。
使用Adobe Acrobat Reader查看此PDF文件时,用户应注意到其中包含内嵌的在线注释,这些注释可能包含了未在正文列出的最新信息或修正。随着后续版本的发布,这些注释将被整合到文档的源文本中,以保持信息的完整性和准确性。
这份e5500RM.pdf文档是嵌入式开发人员不可或缺的参考资料,它不仅涵盖了e5500处理器的基础架构,而且随着技术的演进,不断提供最新更新以帮助开发者解决实际开发中的问题,确保系统的稳定性和性能优化。阅读和理解这些更新内容对于充分利用PowerPC e5500芯片的能力至关重要。
e5500 Core Reference Manual, Rev. 4
xiv Freescale Semiconductor
Contents
Paragraph
Number Title
Page
Number
9.9.5.6 Instruction Jamming Status.................................................................................... 9-44
9.9.5.7 Special Note on Jamming Store Instructions......................................................... 9-45
9.9.5.8 Instruction Jamming Output .................................................................................. 9-45
9.9.5.9 IJAM Procedure ..................................................................................................... 9-45
9.9.5.10 Instruction Jamming Error Conditions .................................................................. 9-47
9.10 Nexus Trace ................................................................................................................... 9-47
9.10.1 Nexus Features........................................................................................................... 9-47
9.10.2 Enabling Nexus Operations on the Core.................................................................... 9-48
9.10.3 Modes of Operation ................................................................................................... 9-48
9.10.4 Supported TCODEs ................................................................................................... 9-49
9.10.5 Nexus Message Fields ............................................................................................... 9-53
9.10.5.1 TCODE Field......................................................................................................... 9-53
9.10.5.2 Source ID Field (SRC)........................................................................................... 9-54
9.10.5.3 Relative Address Field (U-ADDR)........................................................................ 9-54
9.10.5.4 Full Address Field (F-ADDR) ............................................................................... 9-54
9.10.5.5 Timestamp Field (TSTAMP) ................................................................................. 9-54
9.10.6 Nexus Message Queues ............................................................................................. 9-55
9.10.6.1 Message Queue Overrun........................................................................................ 9-55
9.10.6.2 CPU Stall ...............................................................................................................9-56
9.10.6.3 Message Suppression............................................................................................. 9-56
9.10.7 Nexus Message Priority ............................................................................................. 9-56
9.10.7.1 Data Acquisition Message Priority Loss Response and Retry .............................. 9-57
9.10.7.2 Ownership Trace Message Priority Loss Response and Retry .............................. 9-57
9.10.7.3 Program Trace Message Priority Loss Response and Retry.................................. 9-57
9.10.8 Data Trace Message Priority Loss Response and Retry ............................................ 9-58
9.10.9 Debug Status Messages ............................................................................................. 9-58
9.10.10 Error Messages .......................................................................................................... 9-58
9.10.11 Resource Full Messages............................................................................................. 9-58
9.10.12 Program Trace............................................................................................................9-59
9.10.12.1 Enabling and Disabling Program Trace................................................................. 9-59
9.10.12.2 Sequential Instruction Count Field ........................................................................ 9-60
9.10.12.3 Branch/Predicate History Events........................................................................... 9-60
9.10.12.4 Indirect Branch Message Events ........................................................................... 9-60
9.10.12.5 Resource Full Events ............................................................................................. 9-61
9.10.12.6 Program Correlation Events .................................................................................. 9-61
9.10.12.7 Synchronization Conditions................................................................................... 9-61
9.10.13 Data Trace.................................................................................................................. 9-63
9.10.13.1 Enabling and Disabling Data Trace ....................................................................... 9-63
9.10.13.2 Data Trace Range Control ..................................................................................... 9-64
9.10.13.3 Data Trace Size Field (DSZ) ................................................................................. 9-64
9.10.13.4 Data Trace Address Field ...................................................................................... 9-65
e5500 Core Reference Manual, Rev. 4
Freescale Semiconductor xv
Contents
Paragraph
Number Title
Page
Number
9.10.13.5 Data Trace Data Field ............................................................................................ 9-65
9.10.13.6 Data Trace Message Events ................................................................................... 9-65
9.10.14 Ownership Trace........................................................................................................ 9-66
9.10.14.1 Enabling and Disabling Ownership Trace ............................................................. 9-66
9.10.14.2 Ownership Trace Process Field ............................................................................. 9-66
9.10.14.3 Standard Ownership Trace Message Events.......................................................... 9-66
9.10.14.4 “Sync” Ownership Trace Message Events ............................................................ 9-67
9.10.15 Data Acquisition ........................................................................................................ 9-67
9.10.15.1 Enable and Disable Data Acquisition Trace .......................................................... 9-67
9.10.15.2 Data Acquisition ID Tag Field............................................................................... 9-68
9.10.15.3 Data Acquisition Data Field .................................................................................. 9-68
9.10.15.4 Data Acquisition Trace Event................................................................................ 9-68
9.10.16 Watchpoint Trace ....................................................................................................... 9-68
9.10.16.1 Watchpoint Events ................................................................................................. 9-68
9.10.16.2 Enabling and Disabling Watchpoint Trace Messaging.......................................... 9-69
9.10.16.3 Watchpoint Hit Field.............................................................................................. 9-70
9.10.16.4 Watchpoint Trace Message Events ........................................................................ 9-70
9.11 Performance Monitor..................................................................................................... 9-70
9.11.1 Overview.................................................................................................................... 9-70
9.11.2 Performance Monitor Instructions ............................................................................. 9-72
9.11.3 Performance Monitor Interrupt.................................................................................. 9-72
9.11.4 Event Counting .......................................................................................................... 9-73
9.11.4.1 Processor Context Configurability......................................................................... 9-73
9.11.4.2 Core Performance Monitor & PC Capture Function ............................................. 9-74
9.11.5 Examples.................................................................................................................... 9-75
9.11.5.1 Chaining Counters ................................................................................................. 9-75
9.11.5.2 Thresholding .......................................................................................................... 9-76
9.11.6 Event Selection .......................................................................................................... 9-76
Chapter 10
Execution Timing
10.1 Terminology and Conventions ....................................................................................... 10-1
10.2 Instruction Timing Overview......................................................................................... 10-3
10.3 General Timing Considerations ..................................................................................... 10-6
10.3.1 Instruction Fetch Timing Considerations................................................................... 10-7
10.3.1.1 L1 and L2 TLB Access Times............................................................................... 10-8
10.3.1.2 Interrupts Associated with Instruction Fetching.................................................... 10-8
10.3.1.3 Cache-Related Latency.......................................................................................... 10-9
10.3.2 Dispatch, Issue, and Completion Considerations ...................................................... 10-9
10.3.2.1 Instruction Serialization....................................................................................... 10-10
e5500 Core Reference Manual, Rev. 4
xvi Freescale Semiconductor
Contents
Paragraph
Number Title
Page
Number
10.3.3 Memory Synchronization Timing Considerations................................................... 10-11
10.3.3.1 sync Instruction Timing Considerations.............................................................. 10-12
10.3.3.2 mbar Instruction Timing Considerations ............................................................ 10-12
10.4 Execution ..................................................................................................................... 10-13
10.4.1 Branch Unit Execution............................................................................................. 10-13
10.4.1.1 Branch Instructions and Completion ................................................................... 10-13
10.4.1.2 BTB Branch Prediction and Resolution .............................................................. 10-14
10.4.1.2.1 BTB Operations Controlled by BUCSR.......................................................... 10-15
10.4.1.2.2 BTB Special Cases—Phantom Branches and Multiple Matches .................... 10-16
10.4.2 Complex and Simple Unit Execution ...................................................................... 10-16
10.4.2.1 CFX Divide Execution......................................................................................... 10-17
10.4.2.2 CFX Multiply Execution ..................................................................................... 10-18
10.4.2.3 CFX Bypass Path................................................................................................. 10-19
10.4.3 Load/Store Execution .............................................................................................. 10-20
10.4.3.1 Effect of Operand Placement on Performance .................................................... 10-20
10.5 Instruction Latency Summary...................................................................................... 10-21
10.6 Instruction Scheduling Guidelines............................................................................... 10-36
Chapter 11
Core Software Initialization Requirements
11.1 Core State and Suggested Software Initialization After Reset ...................................... 11-1
11.2 MMU State .................................................................................................................... 11-1
11.3 Register State ................................................................................................................. 11-1
11.3.1 GPRs .......................................................................................................................... 11-1
11.3.2 FPRs........................................................................................................................... 11-2
11.3.3 SPRs........................................................................................................................... 11-2
11.3.4 MSR and FPSCR ....................................................................................................... 11-3
11.4 Timer State..................................................................................................................... 11-3
11.5 L1 Cache State ............................................................................................................... 11-4
11.6 L2 Cache State ............................................................................................................... 11-4
11.7 Branch Target Buffer State............................................................................................. 11-5
Appendix A
Revision History
A.1 Changes From Revision 3 to Revision 4......................................................................... A-1
A.2 Changes From Revision 2 to Revision 3......................................................................... A-2
A.3 Changes From Revision 1 to Revision 2......................................................................... A-2
A.4 Changes From Revision 0 to Revision 1......................................................................... A-2
e5500 Core Reference Manual, Rev. 4
Freescale Semiconductor xvii
Contents
Paragraph
Number Title
Page
Number
Appendix B
Simplified Mnemonics
B.1 Overview..........................................................................................................................B-1
B.2 Subtract Simplified Mnemonics ......................................................................................B-1
B.2.1 Subtract Immediate......................................................................................................B-1
B.2.2 Subtract ........................................................................................................................B-2
B.3 Rotate and Shift Simplified Mnemonics..........................................................................B-2
B.3.1 Operations on Words ...................................................................................................B-2
B.3.2 Operations on Double-words.......................................................................................B-3
B.4 Branch Instruction Simplified Mnemonics......................................................................B-4
B.4.1 Key Facts about Simplified Branch Mnemonics .........................................................B-5
B.4.2 Eliminating the BO Operand .......................................................................................B-6
B.4.3 Incorporating the BO Branch Prediction .....................................................................B-7
B.4.4 The BI Operand—CR Bit and Field Representations..................................................B-8
B.4.4.1 BI Operand Instruction Encoding............................................................................B-9
B.4.4.1.1 Specifying a CR Bit.............................................................................................B-9
B.4.4.1.2 The crS Operand ...............................................................................................B-11
B.4.5 Simplified Mnemonics that Incorporate the BO Operand .........................................B-11
B.4.5.1 Examples that Eliminate the BO Operand.............................................................B-12
B.4.6 Simplified Mnemonics that Incorporate CR Conditions (Eliminates BO and Replaces BI
with crS) ................................................................................................................B-15
B.4.6.1 Branch Simplified Mnemonics that Incorporate CR Conditions:
Examples ...........................................................................................................B-17
B.4.6.2 Branch Simplified Mnemonics that Incorporate CR Conditions:
Listings ..............................................................................................................B-17
B.5 Compare Word Simplified Mnemonics .........................................................................B-19
B.6 Compare Doubledoublewordword Simplified Mnemonics ...........................................B-20
B.7 Condition Register Logical Simplified Mnemonics ......................................................B-20
B.8 Trap Instructions Simplified Mnemonics ......................................................................B-21
B.9 Simplified Mnemonics for Accessing SPRs..................................................................B-23
B.10 Recommended Simplified Mnemonics..........................................................................B-23
B.10.1 NOP (nop) .................................................................................................................B-24
B.10.2 Load Immediate (li) ...................................................................................................B-24
B.10.3 Load Address (la) ......................................................................................................B-24
B.10.4 Move Register (mr) ...................................................................................................B-24
B.10.5 Complement Register (not) .......................................................................................B-24
B.10.6 Move to Condition Register (mtcr)...........................................................................B-25
B.10.7 Sync (sync) ................................................................................................................B-25
B.10.8 Integer Select (isel) ....................................................................................................B-25
B.10.9 TLB Invalidate Local Indexed ...................................................................................B-25
e5500 Core Reference Manual, Rev. 4
xviii Freescale Semiconductor
Contents
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