USB 2.0 EHCI 规范详解：增强主机控制器接口

EHCI
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"Enhanced Host Controller Interface for Universal Serial Bus (USB) Revision 2.0 Specification" 《增强型主机控制器接口》(Enhanced Host Controller Interface, EHCI) 是针对USB 2.0规范的一个关键组件，它定义了系统软件与主机控制器硬件之间的硬件/软件接口。该规范详细阐述了在USB 2.0环境中，主机控制器如何处理高速数据传输和与设备的通信。 EHCI是USB 2.0标准的一部分，旨在提高USB的传输速度和效率。在USB 1.1中，最大数据传输速度为12Mbps（低速和全速），而USB 2.0通过引入EHCI，将这个速度提升到了480Mbps（高速）。这显著加快了数据传输速率，使得USB接口能支持更高速度的外设，如硬盘驱动器、打印机和数码相机等。 该规范的日期为2002年3月12日，版本为1.0，涵盖了以下关键内容： 1. **寄存器级接口**：EHCI规范详细定义了用于控制和配置USB主机控制器的一系列寄存器，这些寄存器允许操作系统进行状态查询、命令发送和中断处理。 2. **数据传输机制**：包括异步调度、周期性调度和中断传输模式，以高效地处理不同类型的USB事务。 3. **帧结构**：EHCI使用了一种基于微帧和帧的时间管理结构，以确保高速数据传输的准确性和同步性。 4. **队列首部（Queue Head, QH）**：QH是数据传输的组织单元，它们包含了关于USB设备端点的信息以及传输的参数。 5. **端点处理**：EHCI支持多端点通信，每个端点都有独立的传输队列，增强了系统并行处理能力。 6. **错误处理和恢复**：规范中还包括了错误检测、报告和恢复机制，以确保系统的稳定性和可靠性。 尽管Intel提供了该规格书，但其明确指出该规范“按原样”提供，不提供任何明示或暗示的保修，包括但不限于商品性、非侵权、适合特定目的或任何其他因建议、规范或样本产生的保修。此外，Intel只授予内部复制和重现此规范的许可，而不包含任何知识产权的授权。对于使用该规范可能涉及的任何知识产权侵权，Intel不承担任何责任。用户需根据Intel的销售条款和条件或单独的许可协议获取进一步的授权。 EHCI规范是USB 2.0高速性能的核心，它为开发者和硬件制造商提供了实现高速USB连接的标准框架，促进了USB技术的广泛采用和兼容性。

Enhanced Host Controller Interface Specification for Universal Serial Bus

2008-03-04 上传
Enhanced Host Controller Interface Specification for Universal Serial Bus

1. INTRODUCTION...............................................................................................1
1.1 EHCI Product Compliance.................................................................................................................2
1.2 Architectural Overview.......................................................................................................................2
1.2.1 Interface Architecture....................................................................................................................4
1.2.2 EHCI Schedule Data Structures.....................................................................................................5
1.2.3 Root Hub Emulation......................................................................................................................5
2. REGISTER INTERFACE ..................................................................................7
2.1 PCI Configuration Registers (USB)...................................................................................................8
2.1.1 PWRMGT ? PCI Power Management Interface..........................................................................8
2.1.2 CLASSC ? CLASS CODE REGISTER......................................................................................9
2.1.3 USBBASE ? Register Space Base Address Register..................................................................9
2.1.4 SBRN ? Serial Bus Release Number Register.............................................................................9
2.1.5 Frame Length Adjustment Register (FLADJ)..............................................................................10
2.1.6 Port Wake Capability Register (PORTWAKECAP)...................................................................11
2.1.7 USBLEGSUP ? USB Legacy Support Extended Capability.....................................................11
2.1.8 USBLEGCTLSTS ? USB Legacy Support Control/Status........................................................12
2.2 Host Controller Capability Registers...............................................................................................13
2.2.1 CAPLENGTH ? Capability Registers Length...........................................................................13
2.2.2 HCIVERSION ? Host Controller Interface Version Number....................................................14
2.2.3 HCSPARAMS ? Structural Parameters.....................................................................................14
2.2.4 HCCPARAMS ? Capability Parameters....................................................................................15
2.2.5 HCSP-PORTROUTE ? Companion Port Route Description.....................................................16
2.3 Host Controller Operational Registers............................................................................................17
2.3.1 USBCMD ? USB Command Register.......................................................................................18
2.3.2 USBSTS ? USB Status Register................................................................................................21
2.3.3 USBINTR ? USB Interrupt Enable Register..............................................................................22
2.3.4 FRINDEX ? Frame Index Register............................................................................................23
2.3.5 CTRLDSSEGMENT ? Control Data Structure Segment Register............................................24
2.3.6 PERIODICLISTBASE ? Periodic Frame List Base Address Register......................................24
2.3.7 ASYNCLISTADDR ? Current Asynchronous List Address Register.......................................25
2.3.8 CONFIGFLAG ? Configure Flag Register................................................................................25
2.3.9 PORTSC ? Port Status and Control Register.............................................................................26
3. DATA STRUCTURES.....................................................................................31
3.1 Periodic Frame List...........................................................................................................................31
3.2 Asynchronous List Queue Head Pointer..........................................................................................32
3.3 Isochronous (High-Speed) Transfer Descriptor (iTD)....................................................................33
USB 2.0 i

EHCI Revision 1.0 3/12/2002
3.3.1 Next Link Pointer.........................................................................................................................33
3.3.2 iTD Transaction Status and Control List......................................................................................34
3.3.3 iTD Buffer Page Pointer List (Plus).............................................................................................35
3.4 Split Transaction Isochronous Transfer Descriptor (siTD)...........................................................36
3.4.1 Next Link Pointer.........................................................................................................................37
3.4.2 siTD Endpoint Capabilities/Characteristics.................................................................................37
3.4.3 siTD Transfer State......................................................................................................................38
3.4.4 siTD Buffer Pointer List (plus)....................................................................................................39
3.4.5 siTD Back Link Pointer...............................................................................................................40
3.5 Queue Element Transfer Descriptor (qTD).....................................................................................40
3.5.1 Next qTD Pointer.........................................................................................................................41
3.5.2 Alternate Next qTD Pointer.........................................................................................................41
3.5.3 qTD Token...................................................................................................................................42
3.5.4 qTD Buffer Page Pointer List......................................................................................................45
3.6 Queue Head........................................................................................................................................46
3.6.1 Queue Head Horizontal Link Pointer...........................................................................................46
3.6.2 Endpoint Capabilities/Characteristics..........................................................................................47
3.6.3 Transfer Overlay..........................................................................................................................49
3.7 Periodic Frame Span Traversal Node (FSTN)................................................................................51
3.7.1 FSTN Normal Path Pointer..........................................................................................................51
3.7.2 FSTN Back Path Link Pointer......................................................................................................52
4. OPERATIONAL MODEL................................................................................53
4.1 Host Controller Initialization............................................................................................................53
4.2 Port Routing and Control..................................................................................................................54
4.2.1 Port Routing Control via EHCI Configured (CF) Bit..................................................................55
4.2.2 Port Routing Control via PortOwner and Disconnect Event.......................................................56
4.2.3 Example Port Routing State Machine..........................................................................................57
4.2.4 Port Power....................................................................................................................................57
4.2.5 Port Reporting Over-Current........................................................................................................58
4.3 Suspend/Resume................................................................................................................................59
4.3.1 Port Suspend/Resume..................................................................................................................59
4.4 Schedule Traversal Rules..................................................................................................................61
4.4.1 Example - Preserving Micro-Frame Integrity..............................................................................62
4.5 Periodic Schedule Frame Boundaries vs Bus Frame Boundaries..................................................64
4.6 Periodic Schedule...............................................................................................................................66
4.7 Managing Isochronous Transfers Using iTDs.................................................................................67
4.7.1 Host Controller Operational Model for iTDs...............................................................................67
4.7.2 Software Operational Model for iTDs.........................................................................................69
4.8 Asynchronous Schedule.....................................................................................................................71
4.8.1 Adding Queue Heads to Asynchronous Schedule........................................................................71
4.8.2 Removing Queue Heads from Asynchronous Schedule..............................................................72
4.8.3 Empty Asynchronous Schedule Detection...................................................................................74
ii USB 2.0

EHCI Revision 1.0 3/12/2002
4.8.4 Restarting Asynchronous Schedule Before EOF.........................................................................74
4.8.5 Asynchronous Schedule Traversal : Start Event..........................................................................76
4.8.6 Reclamation Status Bit (USBSTS Register)................................................................................77
4.9 Operational Model for Nak Counter................................................................................................77
4.9.1 Nak Count Reload Control...........................................................................................................78
4.10 Managing Control/Bulk/Interrupt Transfers via Queue Heads....................................................79
4.10.1 Fetch Queue Head........................................................................................................................80
4.10.2 Advance Queue............................................................................................................................81
4.10.3 Execute Transaction.....................................................................................................................81
4.10.4 Write Back qTD...........................................................................................................................86
4.10.5 Follow Queue Head Horizontal Pointer.......................................................................................86
4.10.6 Buffer Pointer List Use for Data Streaming with qTDs...............................................................86
4.10.7 Adding Interrupt Queue Heads to the Periodic Schedule.............................................................88
4.10.8 Managing Transfer Complete Interrupts from Queue Heads.......................................................88
4.11 Ping Control.......................................................................................................................................88
4.12 Split Transactions..............................................................................................................................89
4.12.1 Split Transactions for Asynchronous Transfers...........................................................................90
4.12.2 Split Transaction Interrupt...........................................................................................................92
4.12.3 Split Transaction Isochronous....................................................................................................103
4.13 Host Controller Pause......................................................................................................................114
4.14 Port Test Modes...............................................................................................................................114
4.15 Interrupts..........................................................................................................................................115
4.15.1 Transfer/Transaction Based Interrupts.......................................................................................115
4.15.2 Host Controller Event Interrupts................................................................................................117
5. EHCI EXTENDED CAPABILITIES...............................................................121
5.1 EHCI Extended Capability: Pre-OS to OS Handoff Synchronization........................................121
APPENDIX A. EHCI PCI POWER MANAGEMENT INTERFACE......................125
A.1 PCI Power Management Register Interface..................................................................................125
A.1.1 Power State Transitions.............................................................................................................126
A.1.2 Power State Definitions.............................................................................................................126
A.1.3 PCI PME# Signal.......................................................................................................................127
APPENDIX B. EHCI 64-BIT DATA STRUCTURES............................................129
APPENDIX C. DEBUG PORT.............................................................................133
C.1 Locating the Debug Port..................................................................................................................133
C.2 Using the Debug Port Fields............................................................................................................134
C.3 USB2 Debug Port Register Interface..............................................................................................134
USB 2.0 iii

EHCI Revision 1.0 3/12/2002
C.3.1 Debug Port Control Register......................................................................................................135
C.3.2 USB PIDs Register.....................................................................................................................137
C.3.3 Data Buffer.................................................................................................................................137
C.3.4 Device Address Register............................................................................................................138
C.4 Operational Model...........................................................................................................................138
C.4.1 OUT/SETUP Transactions.........................................................................................................139
C.4.2 IN transactions...........................................................................................................................139
C.4.3 Debug Software Startup.............................................................................................................139
C.4.4 Finding the Debug Peripheral....................................................................................................140
APPENDIX D. HIGH BANDWIDTH ISOCHRONOUS RULES............................141

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