TI-LP8866-Q1：六通道汽车LED背光驱动器详解

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TI-LP8866-Q1是一款专为汽车应用设计的高性能LED背光驱动器，遵循严格的AEC-Q100汽车电子电气合格性标准，确保在严苛的温度范围（-40°C 至 +125°C）内可靠运行。该驱动器具备六个独立的200mA电流通道，每个通道都具有极高的精度，电流匹配度达到1%典型值，这使得它能够实现精细的LED照明控制，例如使用152Hz PWM频率实现32000:1的调光比。 LP8866-Q1内置了升压或SEPIC直流/直流控制器，其工作电压范围宽广，从3V至48V，支持高达2.2MHz的开关频率，有助于降低电磁干扰（EMI）。通过升压同步输入，用户可以灵活设置升压开关频率，或者在不需要升压时自动放电，以节省能源。驱动器还具备自动移相PWM调光功能以及12位模拟调光，提供了丰富的调光选项，提高了系统的灵活性和效率。这款驱动器特别适用于汽车信息娱乐系统、汽车仪表盘、智能车镜和抬头显示器（HUD）等场景中的背光需求。它具有故障诊断功能，能够及时检测和处理潜在问题，确保系统稳定运行。LP8866-Q1采用HTSSOP(38)和QFN(32)两种封装，尺寸分别为9.70mm×4.40mm和5mm×5mm，适合各种小型化设计。其接口包括I²C用于全局LED亮度控制，PWM输入用于精细调节，以及多个GPIO用于模式选择和中断管理。通过这些接口，用户可以轻松地集成和管理复杂的LED照明系统，同时优化功率消耗和电磁兼容性。TI-LP8866-Q1是一款集成了高效升压、精确电流控制和高级调光功能的高性价比汽车级LED驱动器，对于追求性能与节能的汽车电子系统设计来说，是一款理想的选择。

– Optionally, the BST_SYNC can be tied to VDD to enable the boost spread spectrum function or tied to

GND to disable it.

• ISET pin to set the maximum LED current level per string.

7.3.2 Function Setting

Device parameter setting includes:

• BST_FSET pin is used to set the boost switching frequency through a resistor to signal ground.

• PWM_FSET pin is used to set the LED output PWM dimming frequency through a resistor to signal ground.

• MODE pin is used to set the dimming mode via an external resistor to signal ground.

• LED_SET pin is used to set the LED configuration through a resistor to signal ground.

• ISET pin is used to set the maximum LED current level per OUTx pin.

7.3.3 Device Supply (VDD)

All internal analog and digital blocks of LP8866-Q1 are biased from external supply from VDD pin. Either a

typical 5-V or 3.3-V supply rail is able to supply VDD from previous linear regulator or DC/DC converter with at

least 200-mA current capability.

7.3.4 Enable (EN)

The LP8866-Q1 only turns on when the input voltage of EN pin is above the voltage threshold (VEN

) and turns

off when the voltage of EN pin is below the threshold (VEN

). All analog and digital blocks start operating once

the LP8866-Q1 is enabled by asserting EN pin. The SD pin is floating, I2C interface and Fault detection are not

active if the EN pin is de-asserted.

7.3.5 Charge Pump

An integrated regulated charge pump can be used to supply the gate drive for the external FET of the boost

controller. The charge pump is enabled or disabled by automatically detecting whether VDD and CPUMP pin are

connected together. If VDD is < 4.5 V then use the charge pump to generate a 5-V gate voltage to drive the

external boost switching FET. To use the charge pump, a 2.2-µF capacitor is placed between C1N and C1P. If

the charge pump is not required, C1N and C1P could be left unconnected and CPUMP pins tied to VDD. A 4.7-

µF CPUMP capacitor is used to store energy for the gate driver. The CPUMP capacitor is required to be used in

both charge pump enabled and disabled conditions and must be placed as close as possible to the CPUMP

pins.

图 7-1and 图 7-2 show required connections for both use cases.

VDD

ISNSGND

OUT

ISNS

C1N

C1P

CPUMP

PGND

OUT

3.3V

VSENSE_P

VSENSE_N

3 to 48V

VDD

PUMP

FLY

图 7-1. Charge Pump Enabled Circuit

LP8866-Q1

ZHCSKL3B – DECEMBER 2019 – REVISED OCTOBER 2020

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表 7-1. Boost Frequency Selection

R_BST_FSET (kΩ)

BOOST FREQUENCY (kHz)

3.92 400

4.75 200

5.76 303

7.87 100

11 500

17.8 1818

42.2 2000

124 2222

7.3.6.1 Boost Cycle-by-Cycle Current Limit

The voltage between ISNS and ISNSGND is used for both boost DC/DC controller's current sensing and cycle-

by-cycle current limit settings. When the cycle-by-cycle current limit is reached, the controller will turn off the

switching MOSFET immediately and turn on it again in next siwtching cycle. This cycle-by-cycle current limit

could be used as a common protection for all related DC/DC components (inductor, schottky diode and switching

MOSFET) to avoid current running over their max limit. Cycle-by-Cycle current limit won't trigger any faults of the

device.

CYCLE _ LIMIT

ISNS

SENSE

I =

(1)

where

• V

ISNS

= 200 mV

7.3.6.2 Controller Min On/Off time

The device boost DC/DC controller has minimum on/off time as below table. Minimum off time should be

specially taken care in system design. The SW node rising time plus falling time should be higher than minimum

off time to avoid controller not turning off the MOSFET.

表 7-2. Controller Minimum On/Off Time

Frequency (kHz) Minimum Switch OFF time (ns) Minimum Switch ON time (ns)

100 to 500 150 150

1818 to 2222 40 110

7.3.6.3 Boost Adaptive Voltage Control

The LP8866-Q1 boost DC/DC converter generates the anode voltage for the LEDs. During normal operation,

boost output voltage is adjusted automatically based on the LED current sink headroom voltages. This is called

adaptive boost control. The number of used LED outputs is set by LED_SET pin and only the active LED outputs

are monitored to control the adaptive boost voltage. Any LED strings with open or short faults are also removed

from the adaptive voltage control loop. The LED driver pin voltages are periodically monitored by the control loop

and the boost voltage is raised if any of the LED outputs falls below the V

HEADROOM

threshold. The boost voltage

is lowered until any of the LED outputs touch the V

HEADROOM

threshold. See 图 7-4 for how the boost voltage

automatically scales based on the OUTx-pin voltage, V

HEADROOM

and V

HEADROOM_HYS

LP8866-Q1

ZHCSKL3B – DECEMBER 2019 – REVISED OCTOBER 2020

www.ti.com.cn

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