Atheros AR9271: 1x1 2.4GHz 802.11n 无线网卡芯片详细数据表

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"Atheros AR9271 是一款专为2.4GHz 802.11n标准设计的单芯片无线局域网（WLAN）解决方案，集成了MAC、基带、射频、功率放大器和低噪声放大器，并通过USB接口连接。该芯片由Atheros Communications, Inc.制造，主要应用于1x1配置的高性能无线网络设备，旨在为用户提供高速无线连接。" Atheros AR9271无线网卡芯片是一款针对2.4GHz频段的802.11n标准而设计的高性能单芯片解决方案。这个芯片高度集成，包含以下关键组件： 1. **MAC（Media Access Control）**：这是无线网络中的数据链路层的一部分，负责处理帧的传输和接收，确保数据正确无误地发送到目标设备。 2. **基带（Baseband）**：基带处理器负责执行无线信号的数字处理，包括编码、解码以及调制与解调。 3. **射频（Radio）**：射频部分是芯片中的物理层，用于将基带信号转换为无线电磁波进行传输，或者接收无线信号并转化为基带信号。 4. **功率放大器（PA）**：增强无线信号的发射功率，确保信号能够穿透障碍物，达到更远的距离。 5. **低噪声放大器（LNA）**：在接收端，LNA用于放大微弱的无线信号，降低噪声影响，提高接收灵敏度。 6. **USB接口**：AR9271通过USB接口与主机系统连接，简化了硬件设计，便于集成到各种设备中，如笔记本电脑、台式机、路由器等。这款芯片支持802.11n标准，意味着它可以提供最高达300Mbps的理论无线传输速率，相比于802.11g标准有了显著提升。此外，AR9271还可能包括一些Atheros的特色技术，如： - **Atheros SST™（Signal-Sustain Technology™）**：可能是一种信号增强技术，用于改善无线连接的稳定性和性能。 - **Ethos™**：可能是指设备的智能网络管理功能，确保高效和可靠的网络操作。 - **InstallNGo™**：可能是一个快速安装和配置工具，使得用户可以轻松设置和管理无线连接。尽管文档中提到了许多Atheros的注册商标，但具体的实现细节并未在摘要中详述。对于实际应用和故障排查，需要查阅完整的pdf文档以获取更多信息，包括功耗、射频特性、兼容性、功耗管理和其他高级功能。这些详细信息对理解如何优化使用AR9271芯片以及解决可能出现的问题至关重要。

16 • AR9271 Single-Chip 1x1 MAC/BB/Radio for 802.11n WLANs Atheros Communications, Inc.

16 • November 2011 COMPANY CONFIDENTIAL

Atheros Communications, Inc. AR9271 Single-Chip 1x1 MAC/BB/Radio for 802.11n WLANs • 17

COMPANY CONFIDENTIAL November 2011 • 17

3. Medium Access Control (MAC)

The MAC consists of the following major

functional blocks: 10 queue control units

(QCUs), 10 distributed coordination function

(DCF) control units (DCUs), a single DMA Rx

unit (DRU), and a single protocol control unit

(PCU). See Figure 3-1.

3.1 Overview

The MAC block supports full bus-mastering

descriptor-based scatter/gather DMA. Frame

transmission begins with the QCUs. QCUs

manage the DMA of frame data from the host

through the USB interface, and determine

when a frame is available for transmission.

Each QCU targets exactly one DCU. Ready

frames are passed from a QCU to its targeted

DCU. The DCU manages the enhanced

distributed coordination function (EDCF)

channel access procedure on behalf of the

QCUs associated with it.

Functionality of the MAC block includes:

■

Tx frame data transfer from the host to the

radio block using the USB interface

■

Rx frame data transfer from the radio block

to host using the USB interface

■

Interrupt generation and reporting

■

Sleep-mode (power-down) sequencing

■

Miscellaneous error and status reporting

functions

Once the DCU gains access to the channel, it

passes the frame to the PCU, which encrypts

the frame and sends it to the baseband logic.

The PCU handles both processing responses to

the transmitted frame, and reporting the

transmission attempt results to the DCU.

Frame reception begins in the PCU, which

receives the incoming frame bitstream from the

digital PHY. The PCU decrypts the frame and

passes it to the DRU, which manages Rx

descriptors and writes the incoming frame data

and status to the host memory through the USB

interface.

3.2 Descriptor

The MAC is responsible for transferring frames

between the host memory (accessed using the

USB interface) and the AR9281. For all normal

frame transmit/receive activity, the host

provides a series of descriptors to the MAC,

and the MAC then parses the descriptors and

performs the required set of data transfers.

Figure 3-1. MAC Block Diagram

18 • AR9271 Single-Chip 1x1 MAC/BB/Radio for 802.11n WLANs Atheros Communications, Inc.

18 • November 2011 COMPANY CONFIDENTIAL

3.3 Descriptor Format

The transmit (Tx) descriptor format contains

twenty-four 32-bit words and the receive (Rx)

descriptor thirteen 32-bit words (see Table 3-1).

The first two words of the descriptor point to

the next descriptor in the linked list and to the

data buffer associated with the descriptor.

Other words carry additional control

information that affects how the MAC

processes the frame and its data.

A descriptor is required to be aligned on a

32-bit boundary in host memory, although best

performance is achieved if the descriptor is

aligned on a cache-line boundary. The MAC

uses the final two words to report status

information back to the host. See:

Table Description

Table 3 -1 DMA descriptor format

Table 3 -2 Tx control descriptor format

(words 2–13)

Table 3 -3 Tx status descriptors

(words 14–23)

Table 3 -4 Rx control descriptor

(words 2–3)

Table 3 -5 Rx status descriptor

(words 4–12)

Table 3-1. DMA Descriptor Format

Word Bits Field Name Description

0 31:0 link_ptr Link pointer. Contains the address of the next descriptor to be used; must

be 32-bit aligned (bits [1:0] must be 0)

1 31:0 buf_ptr Data buffer pointer. Contains the starting address of the data buffer

associated with this descriptor. A Tx data buffer can begin at any byte

address. A Rx data buffer must be aligned on a 32-bit boundary in host

memory, although best performance is achieved if the Rx data buffer is

cache-line aligned.

(Cache-line size varies from system to system.)

2–13 (Tx)

2–3 (Rx)

31:0 Host-to-

DMA engine

control

information

Additional control information is passed from host to DMA engine. The

format of these words varies depending on whether the descriptor is being

used to Tx a frame from host to PCU, or Rx a frame from PCU to host.

(See Table 3 -2 on page 19, and Table 3-4 on page 29 for details.)

14–23 (Tx)

4–12 (Rx)

31:0 DMA

completion

status

information

Status information reported by the DMA engine when it has finished

processing a descriptor. As with the control information, the format of the

status information differs between Tx and Rx descriptors.

(See Table 3 -3 on page 25, and Table 3-5 on page 29 for details.)

Atheros Communications, Inc. AR9271 Single-Chip 1x1 MAC/BB/Radio for 802.11n WLANs • 19

COMPANY CONFIDENTIAL November 2011 • 19

The Tx descriptor format for words 2 through

13 is described in Table 3-2.

Table 3-2. Tx Control Descriptor Format (Words 2–13)

Word Bits Field Name Description

2 11:0 frame_length Frame length

Specifies the length, in bytes, of the entire MAC frame, including the frame

check sequence (FCS), initialization vector (IV), and integrity check value

(ICV) fields.

12 vmf Virtual more fragment

If this bit is set, bursting is enabled for this frame. If no burst is in progress, it

initiates a CTS-protected burst if cts_enable is set. If a previous burst is in

progress, it ignores the cts_enable bit and assumes the burst is protected.

13 RES Reserved

14 low_rx_chain When set to 1, indicates that the Rx chain mask switches to low power mode

after transmitting this frame

15 clear_retry Setting this bit disables the retry bit from being set in the Tx header on a

frame retry

21:16 tpc_0 Tx power control for series 0

These bits pass unchanged to the baseband, where they are used to control

the transmit power for the frame.

22 rts_enable Request to send (RTS) enable. At most, one of the “rts_enable” and

“cts_enable” bits may be set; it is illegal to set both.

set PCU transmits the frame using the RTS/CTS protocol

clear PCU transmits the frame using the contention/backoff protocol

23 veol Virtual end-of-list flag

When set, indicates that the QCU should act as though the descriptor had a

NULL LinkPtr, even if the LinkPtr is not NULL. Must be valid in the final

descriptor of a frame and must be clear for all other descriptors of the frame.

24 clear_dest_mask Clear destination mask bit flag

If set, instructs the PCU and DCU to clear the destination mask bit at the

index specified by the DestIdx field.

28:25 RES Reserved

29 int_req Interrupt request flag

Set to one by the driver to request that the DMA engine generate an interrupt

upon completion of the frame to which this descriptor belongs.

Note that this field must be valid and identical for all descriptors of the

frame; that is, all descriptors for the frame must have this flag set, or all

descriptors for the frame must have this flag clear.

30 dest_index_valid Destination index valid flag

Specifies whether the contents of the DestIdx field are valid.

31 cts_enable Proceed frame with CTS flag

If set, the PCU first sends a CTS before sending the frame described by the

descriptor. Used for 802.11g and Atheros XR frames to quiet legacy stations

before sending a frame the legacy stations cannot interpret (even at the PHY

level). At most, one of the “rts_enable” and “cts_enable” bits may be set; it is

illegal to set both bits.

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