NXP P4080处理器参考手册更新：2015年修订版修正与增强

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"NXP P4080是一款多核通信处理器，其用户手册修订版2（Rev.2）于2015年9月25日发布，由Freescale Semiconductor提供。此文档主要关注对P4080芯片的更新内容，特别是针对信号字段描述中的修正。在3.6.16节，第183页，关于'信号_B1TTLCRn0字段描述'表中的FLT_SEL设置已更新，推荐设置从旧版本的某个特定值更改为适用于所有协议的"Recommended setting (all protocols): 11"。在3.6.20节，第193页，'信号_B2TTLCRn0字段描述'表中，FLT_SEL的推荐设置同样进行了调整，但没有提及具体的新值，仅表示为"Recommended setting (all protocols)"，表明建议应用于所有协议。这个更新旨在提升处理器的性能和一致性，确保用户能获得最佳的系统操作。值得注意的是，该手册中嵌入了线性笔记形式的更新，用户需通过提供的链接定位到相应页面。为了获得最佳阅读体验，Freescale半导体建议使用Adobe Acrobat Reader来查看此PDF文件，因为后续版本会将这些笔记整合到文档的源文本中。对于使用P4080芯片的开发人员和工程师来说，了解并应用这些更新至关重要，可以避免潜在的问题，并充分利用芯片的全部功能。在阅读和实施这些更改时，务必仔细查阅修订内容，以便确保系统的正确配置和高效运行。此外，由于更新列表可能不完整，用户应保持与厂商的沟通，以获取最新的技术支持和可能的补充说明。"

Section number Title Page

Chapter 9

CoreNet Coherency Fabric (CCF)

9.1 CCF Introduction..........................................................................................................................................................383

9.1.1 CCF Features Summary...............................................................................................................................384

9.2 CoreNet Coherency Fabric (CCF) Memory Map.........................................................................................................385

9.2.1 Snoop ID 0 Port Mapping Register (CCF_SIDMR0)..................................................................................388

9.2.2 Snoop ID n Port Mapping Register (CCF_SIDMRn)..................................................................................389

9.2.3 CSDID 0 Port Mapping Register (CCF_CIDMR0).....................................................................................390

9.2.4 CSDID n Port Mapping Register (CCF_CIDMRn).....................................................................................391

9.2.5 CCF Error Detect Register (CCF_CEDR)...................................................................................................392

9.2.6 CCF Error Enable Register (CCF_CEER)...................................................................................................393

9.2.7 CCF Error Capture Attribute Register (CCF_CECAR)...............................................................................394

9.2.8 CCF Error Capture Address Register High (CCF_CECADRH).................................................................394

9.2.9 CCF Error Capture Address Register Low (CCF_CECADRL)..................................................................395

9.2.10 CCF Error Capture Attribute Register 2 (CCF_CECAR2)..........................................................................395

Chapter 10

Peripheral Access Management Unit (PAMU)

10.1 PAMU Introduction......................................................................................................................................................397

10.1.1 PAMU Overview.........................................................................................................................................397

10.1.2 PAMU Features Summary...........................................................................................................................398

10.2 Data Structures Used by PAMU...................................................................................................................................399

10.2.1 Overview of Data Structures........................................................................................................................399

10.2.1.1 Peripheral Access Authorization and Control Tables (PAACTs)............................................400

10.2.1.2 Operation Mapping Table........................................................................................................401

10.2.1.3 Access Capabilities Across LIODs..........................................................................................401

10.2.2 Structure and Contents of PAACTs.............................................................................................................401

10.2.3 Peripheral Access Authorization and Control Entry (PAACE)...................................................................403

10.2.3.1 PAACE Offset 0x00.................................................................................................................404

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Section number Title Page

10.2.3.2 PAACE Offset 0x08.................................................................................................................406

10.2.3.2.1 PAACE Domain Attributes ..............................................................................407

10.2.3.3 PAACE Offset 0x10.................................................................................................................408

10.2.3.4 PAACE Offset 0x18.................................................................................................................409

10.3 PAMU Memory Map/Register Definitions..................................................................................................................410

10.4 PAMU Memory Map....................................................................................................................................................410

10.4.1 Primary PAACT Base Address High register (PAMUx_PPBAH)..............................................................430

10.4.2 Primary PAACT Base Address Low register (PAMUx_PPBAL)...............................................................431

10.4.3 Primary PAACT Limit Address High register (PAMUx_PPLAH).............................................................431

10.4.4 Primary PAACT Limit Address Low register (PAMUx_PPLAL)..............................................................432

10.4.5 Secondary PAACT Base Address High register (PAMUx_SPBAH)..........................................................432

10.4.6 Secondary PAACT Base Address Low register (PAMUx_SPBAL)...........................................................433

10.4.7 Secondary PAACT Limit Address High register (PAMUx_SPLAH).........................................................433

10.4.8 Secondary PAACT Limit Address Low register (PAMUx_SPLAL)..........................................................433

10.4.9 OMT Base Address High register (PAMUx_OBAH)..................................................................................434

10.4.10 OMT Base Address Low register (PAMUx_OBAL)...................................................................................434

10.4.11 OMT Limit Address High register (PAMUx_OLAH).................................................................................435

10.4.12 OMT Limit Address Low register (PAMUx_OLAL)..................................................................................435

10.4.13 PAMU Address Capabilities Register 1 (PAMUx_PAC1)..........................................................................436

10.4.14 PAMU Address Capabilities Register 2 (PAMUx_PAC2)..........................................................................436

10.4.15 PAMU Operation Error Status register 1 (PAMUx_POES1)......................................................................437

10.4.16 PAMU Operation Error Status register 2 (PAMUx_POES2)......................................................................438

10.4.17 PAMU Operation Error Address High register (PAMUx_POEAH)...........................................................438

10.4.18 PAMU Operation Error Address Low register (PAMUx_POEAL)............................................................439

10.4.19 Access Violation Status register 1 (PAMUx_AVS1)..................................................................................440

10.4.20 Access Violation Status register 2 (PAMUx_AVS2)..................................................................................442

10.4.21 Access Violation Address High register (PAMUx_AVAH)........................................................................443

10.4.22 Access Violation Address Low register (PAMUx_AVAL).........................................................................443

10.4.23 ECC Error Control Register (PAMUx_EECTL).........................................................................................443

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Section number Title Page

10.4.24 ECC Error Interrupt Enable Register (PAMUx_EEINTEN).......................................................................444

10.4.25 ECC Error Detect Register (PAMUx_EEDET)...........................................................................................445

10.4.26 ECC Error Attributes Register (PAMUx_EEATTR)...................................................................................446

10.4.27 ECC Error Address High (PAMUx_EEAHI)..............................................................................................447

10.4.28 ECC Error Address Low (PAMUx_EEALO)..............................................................................................447

10.4.29 ECC Error Data High (PAMUx_EEDHI)....................................................................................................448

10.4.30 ECC Error Data Low (PAMUx_EEDLO)...................................................................................................448

10.4.31 Unauthorized device access detection register (PAMUx_UDAD)..............................................................449

10.4.32 PAMU Revision register 1 (PAMUx_PR1).................................................................................................449

10.4.33 PAMU Revision register 2 (PAMUx_PR2).................................................................................................450

10.4.34 PAMU Capabilities register 1 (PAMUx_PC1)............................................................................................450

10.4.35 PAMU Capabilities register 2 (PAMUx_PC2)............................................................................................451

10.4.36 PAMU Capabilities register 3 (PAMUx_PC3)............................................................................................452

10.4.37 PAMU Capabilities register 4 (PAMUx_PC4)............................................................................................454

10.4.38 PAMU Control register (PAMUx_PC)........................................................................................................455

10.4.39 PAMU Interrupt Control and Status register (PAMUx_PICS)....................................................................456

10.5 PAMU Functional Description.....................................................................................................................................457

10.5.1 System Set-Up for PAMU Operation..........................................................................................................457

10.5.2 Steps in Processing of DSA Operations by PAMU.....................................................................................458

10.5.3 Detailed Description of PAMU Actions......................................................................................................460

10.5.3.1 PAMU Gate Closed and PAMU Enable Check.......................................................................460

10.5.3.2 PPAACT Request Range Check..............................................................................................461

10.5.3.3 PPAACT Cache Lookup..........................................................................................................462

10.5.3.4 PAMU Fetch Request..............................................................................................................462

10.5.3.5 Primary PAACE Processing....................................................................................................462

10.5.3.6 SPAACE Access and Processing.............................................................................................464

10.5.3.6.1 SPAACT Request Range Check.......................................................................464

10.5.3.6.2 SPAACT Cache Lookup Request.....................................................................465

10.5.3.6.3 Secondary PAACE Processing.........................................................................465

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Section number Title Page

10.5.3.7 Address Translation Service....................................................................................................466

10.5.3.7.1 No Address Translation Mode..........................................................................466

10.5.3.7.2 Window Address Translation Mode.................................................................467

10.5.3.8 OMT Access and Service.........................................................................................................469

10.5.3.8.1 No Operation Translation.................................................................................469

10.5.3.8.2 Operation Type Translation..............................................................................470

10.5.3.8.3 OMT Cache Access..........................................................................................472

10.5.3.9 Access Violation......................................................................................................................473

10.6 PAMU Initialization/Application Information.............................................................................................................473

10.6.1 System Set-Up..............................................................................................................................................473

10.6.1.1 Setting Up PAMU....................................................................................................................473

10.6.1.2 Power-On Reset.......................................................................................................................474

10.6.2 System with Multiple PAMUs ....................................................................................................................474

10.6.2.1 PAACT Locations....................................................................................................................474

10.6.2.2 OMT Locations........................................................................................................................475

10.6.2.3 Location of PAACT and OMT Data Structures.......................................................................475

10.6.3 Peer-to-Peer I/O Operations.........................................................................................................................475

10.6.4 PAMU Cache Coherency.............................................................................................................................476

10.6.5 Quiescing I/O Devices.................................................................................................................................476

10.6.5.1 Quiescing I/O Devices for Table/Entry Updates.....................................................................477

10.6.5.2 Quiescing I/O Devices for Enabling PAMU and its Caches...................................................477

10.6.6 Locality of References.................................................................................................................................477

10.6.6.1 Spatial Locality........................................................................................................................477

10.6.6.2 Temporal Locality....................................................................................................................478

10.6.7 Recovering Address Space...........................................................................................................................478

10.6.7.1 Primary PAACT Address Window..........................................................................................478

10.6.7.2 Secondary PAACT Address Window......................................................................................478

10.6.7.3 Secondary Sub-Windows and PAACEs..................................................................................478

10.6.8 Data Structure Size and Alignment..............................................................................................................479

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Section number Title Page

10.7 PAMU Setup.................................................................................................................................................................479

10.7.1 PAMU Operation Encoding.........................................................................................................................479

10.7.1.1 Ingress Operation Encoding (IOE)..........................................................................................480

10.7.1.2 Egress Operation Encodings....................................................................................................480

10.7.1.3 IOE to EOE Translations.........................................................................................................482

10.7.1.3.1 PAMU Bypass Mode and No Operation Translation Mode.............................482

10.7.1.3.2 Immediate and Indexed Operation Translation Modes.....................................483

10.7.2 Domain Attributes........................................................................................................................................483

10.7.2.1 Constrained Domain Attribute.................................................................................................483

10.7.3 Implementation Attributes...........................................................................................................................484

10.7.4 Operation Mapping Table (OMT)................................................................................................................484

Chapter 11

DDR Memory Controller

11.1 DDR Introduction.........................................................................................................................................................485

11.2 DDR Features Summary...............................................................................................................................................486

11.2.1 DDR Modes of Operation............................................................................................................................487

11.3 DDR External Signal Descriptions...............................................................................................................................487

11.3.1 DDR Signals Overview................................................................................................................................487

11.3.2 DDR Detailed Signal Descriptions..............................................................................................................488

11.3.2.1 Memory Interface Signals........................................................................................................488

11.3.2.2 Clock Interface Signals............................................................................................................493

11.4 DDR Memory Controller Memory Map.......................................................................................................................494

11.4.1 Chip select n memory bounds (DDRx_CSn_BNDS)..................................................................................499

11.4.2 Chip select n configuration (DDRx_CSn_CONFIG)...................................................................................500

11.4.3 Chip select n configuration 2 (DDRx_CSn_CONFIG_2)............................................................................502

11.4.4 DDR SDRAM timing configuration 3 (DDRx_TIMING_CFG_3).............................................................503

11.4.5 DDR SDRAM timing configuration 0 (DDRx_TIMING_CFG_0).............................................................505

11.4.6 DDR SDRAM timing configuration 1 (DDRx_TIMING_CFG_1).............................................................508

11.4.7 DDR SDRAM timing configuration 2 (DDRx_TIMING_CFG_2).............................................................512

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