摩托罗拉与IBM开发的PowerPC 32位微处理器编程环境概览

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"《POWER PC编程环境.pdf》是一份由摩托罗拉和IBM联合开发的文档，聚焦于32位微处理器编程环境。这份文档详述了PowerPC微处理器家族的特性与编程工具，目的是为了帮助系统和软件开发者充分利用这种技术。由于产品尚在开发阶段，摩托罗拉和IBM保留在未通知的情况下更改或停止该产品的权利。文档涵盖了MPCFPE32B/AD版本，时间戳为1997年，修订至第一版，强调了PowerPC商标权属于摩托罗拉公司和国际商业机器公司（IBM）。版权和专利声明明确指出，虽然信息被提供用于设计和实现基于PowerPC的系统和软件，但并未授予用户直接或间接的版权或专利许可，以修改微处理器设计或制造电路。 PowerPC微处理器家族集成了摩托罗拉和IBM的知识产权，但双方对市场上的性能、操作或其他特性并不承担任何责任或担保。它们之间不存在代理关系，各自独立行事，第三方同样如此。这份文档的主要内容包括但不限于硬件规格、软件开发工具接口（例如调试器、编译器和链接器）、性能优化技巧以及可能的体系结构细节，所有这些都是为了让工程师们能够高效地进行软件开发，并且适应PowerPC架构的特殊需求。对于潜在的开发者来说，阅读这份文档至关重要，因为它提供了关于PowerPC平台的基础知识，如指令集架构、数据类型、内存管理、中断处理以及与操作系统和设备驱动程序的交互。同时，它还可能涉及编程模型、性能基准测试以及如何处理移植性问题，以便在实际项目中实现无缝集成。尽管文档是针对特定时期的产品，但它所阐述的概念和技术原理在当时的IT领域具有重要价值，对于理解PowerPC处理器及其生态系统的历史演变仍有参考意义。随着技术的发展，这份文档可能会成为研究早期PowerPC编程实践和历史的宝贵资料。"

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xiv

PowerPC Microprocessor Family: The Programming Environments (32-Bit)

CONTENTS

Paragraph

Number

Title

Page

Number

Appendix F

Simplified Mnemonics

F.1 Symbols ...............................................................................................................F-1

F.2 Simplified Mnemonics for Subtract Instructions.................................................F-2

F.2.1 Subtract Immediate..........................................................................................F-2

F.2.2 Subtract............................................................................................................F-2

F.3 Simplified Mnemonics for Compare Instructions................................................F-3

F.3.1 Word Comparisons ..........................................................................................F-3

F.4 Simplified Mnemonics for Rotate and Shift Instructions ....................................F-4

F.4.1 Operations on Words .......................................................................................F-4

F.5 Simplified Mnemonics for Branch Instructions...................................................F-6

F.5.1 BO and BI Fields .............................................................................................F-6

F.5.2 Basic Branch Mnemonics................................................................................F-6

F.5.3 Branch Mnemonics Incorporating Conditions...............................................F-12

F.5.4 Branch Prediction ..........................................................................................F-17

F.6 Simplified Mnemonics for Condition Register Logical Instructions.................F-18

F.7 Simplified Mnemonics for Trap Instructions.....................................................F-19

F.8 Simplified Mnemonics for Special-Purpose Registers ......................................F-21

F.9 Recommended Simplified Mnemonics..............................................................F-23

F.9.1 No-Op (

nop

) ..................................................................................................F-23

F.9.2 Load Immediate (

) .......................................................................................F-23

F.9.3 Load Address

(la)

..........................................................................................F-23

F.9.4 Move Register (

).......................................................................................F-23

F.9.5 Complement Register (

not

) ...........................................................................F-24

F.9.6 Move to Condition Register (

mtcr

)...............................................................F-24

Glossary of Terms and Abbreviations

Index

Illustrations

ILLUSTRATIONS

Figure

Number

Title

Page

Number

1-1 Programming Model—PowerPC Registers ..........................................................1-8

1-2 Big-Endian Byte and Bit Ordering...................................................................... 1-10

2-1 UISA Programming Model—User-Level Registers ............................................. 2-2

2-2 General-Purpose Registers (GPRs) .......................................................................2-4

2-3 Floating-Point Registers (FPRs)............................................................................ 2-5

2-4 Condition Register (CR)........................................................................................ 2-5

2-5 Floating-Point Status and Control Register (FPSCR)........................................... 2-8

2-6 XER Register....................................................................................................... 2-11

2-7 Link Register (LR) .............................................................................................. 2-12

2-8 Count Register (CTR) ......................................................................................... 2-12

2-9 VEA Programming Model—User-Level Registers Plus Time Base .................. 2-14

2-10 Time Base (TB)................................................................................................... 2-15

2-11 OEA Programming Model—All Registers ......................................................... 2-18

2-12 Machine State Register (MSR) ...........................................................................2-21

2-13 Processor Version Register (PVR)...................................................................... 2-23

2-14 Upper BAT Register............................................................................................ 2-24

2-15 Lower BAT Register...........................................................................................2-24

2-16 SDR1...................................................................................................................2-27

2-17 Segment Register Format (T = 0)........................................................................ 2-28

2-18 Segment Register Format (T = 1)........................................................................ 2-28

2-19 Data Address Register (DAR)............................................................................. 2-29

2-20 SPRG0–SPRG3................................................................................................... 2-30

2-21 DSISR.................................................................................................................. 2-30

2-22 Machine Status Save/Restore Register 0 (SRR0) ............................................... 2-31

2-23 Machine Status Save/Restore Register 1 (SRR1) ............................................... 2-31

2-24 Decrementer Register (DEC) .............................................................................. 2-33

2-25 Data Address Breakpoint Register (DABR) ....................................................... 2-34

2-26 External Access Register (EAR)......................................................................... 2-35

3-1 C Program Example—Data Structure S................................................................ 3-3

3-2 Big-Endian Mapping of Structure

...................................................................... 3-4

3-3 Little-Endian Mapping of Structure

................................................................... 3-5

3-4 Little-Endian Mapping of Structure

—Alternate View...................................... 3-6

3-5 Munged Little-Endian Structure

as Seen by the Memory Subsystem ............... 3-7

3-6 Munged Little-Endian Structure

as Seen by Processor...................................... 3-8

3-7 True Little-Endian Mapping, Word Stored at Address 05.................................... 3-9

3-8 Word Stored at Little-Endian Address 05 as Seen by the Memory Subsystem.. 3-10

xvi

PowerPC Microprocessor Family: The Programming Environments (32-Bit)

ILLUSTRATIONS

Figure

Number

Title

Page

Number

3-9 Floating-Point Single-Precision Format.............................................................. 3-16

3-10 Floating-Point Double-Precision Format ............................................................ 3-16

3-11 Approximation to Real Numbers ........................................................................ 3-18

3-12 Format for Normalized Numbers ........................................................................3-19

3-13 Format for Zero Numbers ................................................................................... 3-20

3-14 Format for Denormalized Numbers .................................................................... 3-20

3-15 Format for Positive and Negative Infinities ........................................................3-21

3-16 Format for NaNs.................................................................................................. 3-21

3-17 Representation of Generated QNaN.................................................................... 3-22

3-18 Single-Precision Representation in an FPR ........................................................3-25

3-19 Relation of Z1 and Z2 ......................................................................................... 3-26

3-20 Selection of Z1 and Z2 for the Four Rounding Modes ....................................... 3-27

3-21 Rounding Flags in FPSCR .................................................................................. 3-28

3-22 Floating-Point Status and Control Register (FPSCR)......................................... 3-28

3-23 Initial Flow for Floating-Point Exception Conditions......................................... 3-36

3-24 Checking of Remaining Floating-Point Exception Conditions........................... 3-40

4-1 Register Indirect with Immediate Index Addressing for Integer Loads/Stores... 4-29

4-2 Register Indirect with Index Addressing for Integer Loads/Stores.....................4-30

4-3 Register Indirect Addressing for Integer Loads/Stores....................................... 4-31

4-4 Register Indirect with Immediate Index Addressing for

Floating-Point Loads/Stores............................................................................ 4-37

4-5 Register Indirect with Index Addressing for Floating-Point Loads/Stores......... 4-38

4-6 Branch Relative Addressing................................................................................ 4-42

4-7 Branch Conditional Relative Addressing............................................................ 4-43

4-8 Branch to Absolute Addressing........................................................................... 4-43

4-9 Branch Conditional to Absolute Addressing....................................................... 4-44

4-10 Branch Conditional to Link Register Addressing ............................................... 4-45

4-11 Branch Conditional to Count Register Addressing............................................. 4-46

6-1 Machine Status Save/Restore Register 0............................................................. 6-15

6-2 Machine Status Save/Restore Register 1............................................................. 6-15

6-3 Machine State Register (MSR) ...........................................................................6-15

7-1 MMU Conceptual Block Diagram........................................................................7-6

7-2 Address Translation Types.................................................................................... 7-8

7-3 General Flow of Address Translation (Real Addressing Mode and Block) ....... 7-12

7-4 General Flow of Page and Direct-Store Address Translation............................. 7-13

7-5 BAT Array Organization..................................................................................... 7-21

7-6 BAT Array Hit/Miss Flow .................................................................................. 7-23

7-7 Format of Upper BAT Registers.........................................................................7-25

7-8 Format of Lower BAT Registers......................................................................... 7-25

7-9 Memory Protection Violation Flow for Blocks................................................... 7-30

7-10 Block Physical Address Generation.................................................................... 7-31

7-11 Block Address Translation Flow......................................................................... 7-32

7-12 Page Address Translation Overview................................................................... 7-35

Illustrations

xvii

ILLUSTRATIONS

Figure

Number

Title

Page

Number

7-13 Segment Register Format for Page Address Translation .................................... 7-35

7-14 Page Table Entry Format..................................................................................... 7-37

7-15 Memory Protection Violation Flow for Pages .................................................... 7-45

7-16 Page Address Translation Flow—TLB Hit......................................................... 7-47

7-17 Page Memory Protection Violation Conditions for Page Address Translation .. 7-48

7-18 Page Table Definitions........................................................................................ 7-49

7-19 SDR1 Register Format ........................................................................................ 7-50

7-20 Hashing Functions for Page Tables..................................................................... 7-53

7-21 Generation of Addresses for Page Tables ........................................................... 7-55

7-22 Example Page Table Structure ............................................................................7-57

7-23 Example Primary PTEG Address Generation..................................................... 7-59

7-24 Example Secondary PTEG Address Generation................................................. 7-60

7-25 Page Table Search Flow...................................................................................... 7-63

7-26 Segment Register Format for Direct-Store Segments......................................... 7-68

7-27 Direct-Store Segment Translation Flow.............................................................. 7-71

8-1 Instruction Description.......................................................................................... 8-9

D-1 IEEE 64-Bit Execution Model ............................................................................. D-1

D-2 Multiply-Add 64-Bit Execution Model................................................................ D-4

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