MIPI D-PHY 2.0：智能手机与汽车应用的高速低功耗解决方案

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MIPI-D-PHY是2007年MIPI Alliance发布的一项关键接口标准，它专为智能手机中的摄像头和显示模块设计，因其灵活性、高速度、低功耗和成本效益而备受青睐。该标准允许在诸如汽车摄像头感知系统、碰撞避免雷达、车内娱乐与仪表盘显示器等众多应用领域实现高效通信。作为MIPI（移动接口物理联盟）的一种规范，MIPI D-PHY v0.90.00包含了对硬件制造商的重要指导和注意事项。该版本被MIPI董事会采纳，遵循MIPI会员协议和章程中的条款。实施者和审查者需注意，这是MIPI PHY工作组（Working Group）建议的稳定且可靠的版本，旨在促进一致性。之前的版本D-PHY v0.65已被v0.90.00取代，不推荐再进行实施。尽管如此，MIPI Alliance强调，D-PHY v0.90.00的技术基础被认为是稳定的，未来可能不会有重大功能变化。截至2007年11月，已知的讨论点主要是可能导致增量改进的潜在议题。若进行任何变更，这些讨论将作为后续修订的基础。在实际应用中，为了确保兼容性和性能，制造商应基于v0.90.00进行开发工作，并密切关注MIPI Alliance的更新通知。这有助于保持系统的长期兼容性，同时适应不断发展的技术需求。对于那些考虑采用MIPI D-PHY的公司来说，理解并遵循这一规范至关重要，以确保产品的竞争力和市场接受度。此外，随着汽车电子和物联网等领域的发展，MIPI D-PHY可能会持续优化以适应这些新兴市场的高数据速率和低功耗要求。

Version 0.90.00 8-Oct-2007 MIPI Alliance Specification for D-PHY

MIPI Alliance Member Confidential.

MIPI Alliance Specification for D-PHY 278

1 Overview 279

This specification provides a flexible, low-cost, High-Speed serial interface solution for communication 280

interconnection between components inside a mobile device. Traditionally, these interfaces are CMOS 281

parallel busses at low bit rates with slow edges for EMI reasons. The D-PHY solution enables significant 282

extension of the interface bandwidth for more advanced applications. The D-PHY solution can be realized 283

with very low power consumption. 284

1.1 Scope 285

The scope of this document is to specify the lowest layers of High-Speed source-synchronous interfaces to 286

be applied by MIPI Alliance application or protocol level specifications. This includes the physical 287

interface, electrical interface, low-level timing and the PHY-level protocol. These functional areas taken 288

together are known as D-PHY. 289

The D-PHY specification shall always be used in combination with a higher layer MIPI specification that 290

references this specification. Initially, this specification will be used for the connection of a host processor 291

to display and camera modules as used in mobile devices. However, this specification can also be 292

referenced by other upcoming MIPI Alliance specifications. 293

The following topics are outside the scope of this document: 294

• Explicit specification of signals of the clock generator unit. Of course, the D-PHY 295

specification does implicitly require some minimum performance from the clock signals. 296

Intentionally, only the behavior on the interface pins is constrained. Therefore, the clock 297

generation unit is excluded from this specification, and will be a separate functional unit that 298

provides the required clock signals to the D-PHY in order to meet the specification. This allows 299

all kinds of implementation trade-offs as long as these do not violate this specification. More 300

information can be found in section 4. 301

• Test modes, patterns, and configurations. Obviously testability is very im

portant, but because 302

the items to test are mostly application specific or implementation related, the specification of 303

tests is deferred to either the higher layer specifications or the product specification. Furthermore 304

MIPI D-PHY compliance testing is not included in this specification. 305

• Procedure to resolve contention situations. The D-PHY contains several mechanisms to detect 306

Link contention. However, certain contention situations can only be detected at higher levels and 307

are therefore not included in this specification. 308

• Ensure proper operation of a connection between different Lane Module types. There are 309

several different Lane Module types to optimally support the different functional requirements of 310

several applications. This means that next to some base-functionality there are optional features 311

which can be included or excluded. This specification only ensures correct operation for a 312

connection between matched Lane Modules types, which means: Modules that support the same 313

features and have complementary functionality. In case the two sides of the Lane are not the same 314

type, and these are supposed to work correctly, it shall be ensured by the manufacturer(s) of the 315

Lane Module(s) that the provided additional functionality does not corrupt operation. This can be 316

easiest accomplished if the additional functionality can be disabled by other means independent of 317

the MIPI D-PHY interface, such that the Lane Modules behave as if they were the same type. 318

• ESD protection level of the IO. The required level will depend on a particular application 319

environment and product type. 320

Version 0.90.00 8-Oct-2007 MIPI Alliance Specification for D-PHY

MIPI Alliance Member Confidential.

• Exact Bit-Error-Rate (BER) value. The actual value of the achieved BER depends on the total 321

system integration and the hostility of the environment. Therefore, it is impossible to specify a 322

BER for individual parts of the Link. This specification allows for implementations with a 323

BER<10

-12

. 324

• Specification of the PHY-Protocol Interface. The D-PHY specification includes a PHY-325

Protocol Interface (PPI) annex that provides one possible solution for this interface. This annex is 326

limited to the essential signals for normal operation in order to clarify the kind of signals needed 327

at this interface. For power reasons this interface will be internal for most applications. Practical 328

implementations may be different without being inconsistent with the D-PHY specification. 329

• Implementations. This specification is intended to restrict the implementation as little as 330

possible. Various sections of this specification use block diagrams or example circuits to illustrate 331

the concept and are not in any way claimed to be the preferred or required implementation. Only 332

the behavior on the D-PHY interface pins is normative. 333

Regulatory compliance methods are not within the scope of this document. It is the responsibility of 334

product manufacturers to ensure that their designs comply with all applicable regulatory requirements. 335

1.2 Purpose 336

The D-PHY specification is used by manufacturers to design products that adhere to MIPI Alliance 337

interface specifications for mobile device such as, but not limited to, camera, display and unified protocol 338

interfaces. 339

Implementing this specification reduces the time-to-market and design cost of mobile devices by 340

standardizing the interface between products from different manufacturers. In addition, richer feature sets 341

requiring high bit rates can be realized by implementing this specification. Finally, adding new features to 342

mobile devices is simplified due to the extensible nature of the MIPI Alliance Specifications. 343

344

Version 0.90.00 8-Oct-2007 MIPI Alliance Specification for D-PHY

MIPI Alliance Member Confidential.

2 Terminology 345

The MIPI Alliance has adopted Section 13.1 of the IEEE Standards Style Manual, which dictates use of the 346

words “shall”, “should”, “may”, and “can” in the development of documentation, as follows: 347

The word shall is used to indicate mandatory requirements strictly to be followed in 348

order to conform to the standard and from which no deviation is permitted (shall equals 349

is required to). 350

The use of the word must is deprecated and shall not be used when stating mandatory 351

requirements; must is used only to describe unavoidable situations. 352

The use of the word will is deprecated and shall not be used when stating mandatory 353

requirements; will is only used in statements of fact. 354

The word should is used to indicate that among several possibilities one is recommended 355

as particularly suitable, without mentioning or excluding others; or that a certain course 356

of action is preferred but not necessarily required; or that (in the negative form) a certain 357

course of action is deprecated but not prohibited (should equals is recommended that). 358

The word may is used to indicate a course of action permissible within the limits of the 359

standard (may equals is permitted). 360

The word can is used for statements of possibility and capability, whether material, 361

physical, or causal (can equals is able to). 362

Throughout this document, the chronology for binary sequences and timing diagrams is from left (first in 363

time) to right (later in time), unless otherwise specified. 364

This document uses the C/Verilog representation for operators where bitwise AND is represented by ‘&’, 365

bitwise OR is represented by ‘|’, bitwise exclusive-OR is represented by ‘^’ and 1’s complement (negation) 366

is represented by ‘~’. 367

All sections are normative, unless they are explicitly indicated to be informative. 368

2.1 Definitions 369

Bi-directional: A single Data Lane that supports communication in both the Forward and Reverse 370

directions. 371

DDR Clock: Half rate clock used for dual-edged data transmission. 372

D-PHY: The source synchronous PHY defined in this document. D-PHYs communicate on the order of 373

500 Mbit/s hence the Roman numeral for 500 or “D.” 374

Escape Mode: An optional mode of operation for Data Lanes that allows low bit-rate commands and data 375

to be transferred at very low power. 376

Forward Direction: The signal direction is defined relative to the direction of the High-Speed DDR clock. 377

Transmission from the side sending the clock to the side receiving the clock is the Forward direction. 378

Version 0.90.00 8-Oct-2007 MIPI Alliance Specification for D-PHY

MIPI Alliance Member Confidential.

Lane: Consists of two complementary Lane Modules communicating via two-line, point-to-point Lane 379

Interconnects. Sometimes Lane is also used to denote interconnect only. A Lane can be used for either Data 380

or Clock signal transmission. 381

Lane Interconnect: Two-line, point-to-point interconnect used for both differential High-Speed signaling 382

and Low-Power, single-ended signaling. 383

Lane Module: Module at each side of the Lane for driving and/or receiving signals on the Lane. 384

Line: An interconnect wire used to connect a driver to a receiver. Two Lines are required to create a Lane 385

Interconnect. 386

Link: A connection between two devices containing one Clock Lane and at least one Data Lane. A Link 387

consists of at least two PHYs and two Lane Interconnects. 388

Master: The Master side of a Link is defined as the side that transmits the High-Speed Clock. The Master 389

side transmits data in the Forward direction. 390

PHY: A functional block that implements the features necessary to communicate over the Lane 391

Interconnect. A PHY consists of one Lane Module configured as a Clock Lane, one or more Lane Modules 392

configured as Data Lanes and a PHY Adapter Layer. 393

PHY Adapter: A protocol layer that converts symbols from an APPI to the signals used by a specific PHY 394

PPI. 395

PHY Configuration: A set of Lanes that represent a possible Link. A PHY configuration consists of a 396

minimum of two Lanes, one Clock Lane and one or more Data Lanes. 397

Reverse Direction: Reverse direction is the opposite of the forward direction. See the description for 398

Forward Direction. 399

Slave: The Slave side of a Link is defined as the side that does not transmit the High-Speed Clock. The 400

Slave side may transmit data in the Reverse direction. 401

Turnaround: Reversing the direction of communication on a Data Lane. 402

Unidirectional: A single Lane that supports communication in the Forward direction only. 403

2.2 Abbreviations 404

e.g. For example (Latin: exempli gratia) 405

i.e. That is (Latin: id est) 406

2.3 Acronyms 407

APPI Abstracted PHY-Protocol Interface 408

BER Bit Error Rate 409

CIL Control and Interface Logic 410

DDR Double Data Rate 411

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