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首页2014款MacBook Pro与iMac Pro原理图详解
2014款MacBook Pro与iMac Pro原理图详解
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更新于2024-07-18
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本文档主要探讨的是2014款MacBook Pro和iMac Pro的苹果电脑原理图,这两款高端产品是苹果电脑系列中的旗舰型号。在2014年,苹果推出了多款创新性的设计,如Retina显示屏、强大的处理器和优化的散热系统,这些都在这款原理图中得到了体现。
MacBook Pro的原理图包括了以下几个关键部分:
1. 外壳与结构:展示了笔记本电脑的外壳材料选择、主板布局以及内部机械结构,如铰链、键盘和触摸板的设计。
2. 显示技术:着重介绍了Retina显示屏的组成,包括像素排列、色彩管理和背光系统,这些都是提高视觉体验的关键组件。
3. 处理器和图形处理器:文档深入解析了Intel Core i系列处理器和AMD Radeon Pro显卡的集成方式,强调了它们在处理性能和图形渲染上的优势。
4. 存储与内存:涵盖了SSD硬盘、内存模块以及Thunderbolt接口的连接方式,展示了数据传输速度的提升。
5. 内部连接与信号路径:展示了电路板上各类接口(如USB、Thunderbolt、HDMI等)的布局,以及无线通信模块(Wi-Fi和蓝牙)的工作原理。
6. 供电与散热系统:详细讲解了电池、电源管理芯片以及散热片、风扇的设计,确保高性能运行时的稳定性和持久性。
7. 安全与输入设备:涉及指纹识别传感器、面部识别技术以及键盘和触控板的敏感度和响应机制。
8. 软件与硬件交互:讨论了操作系统(OS X Yosemite)如何与硬件紧密协作,以实现无缝用户体验。
iMac Pro则在设计理念上有所突破,作为一体机,其原理图会涵盖:
1. 一体化设计:强调显示器、主机和音频系统的一体化集成,减少了外部组件的需求。
2. 高端组件:如搭载了Intel Xeon处理器、AMD Vega显卡以及大容量内存的内部配置。
3. 显示技术:同样注重显示质量,可能包含OLED或量子点显示器的特性和技术细节。
4. 内部连接:由于一体机的紧凑性,文档会关注电缆管理和内部布线的设计。
5. 多用途接口:对于iMac Pro的Thunderbolt 3和USB-C接口,如何支持外接多个设备和扩展功能的分析。
6. 散热解决方案:考虑到一体机内部空间有限,高效的散热系统设计至关重要。
7. 专业级硬件支持:如用于视频编辑、3D建模和图形渲染的特殊硬件配置。
通过阅读这份2014款MacBook Pro和iMac Pro的原理图,用户可以深入了解苹果电脑内部构造和工作原理,对于维修、升级或者深度定制电脑具有重要的参考价值。同时,它也反映了苹果公司在设计上的追求,即高性能、优雅外观和用户友好的体验。
OUT
IN
IN
IN
OUT
IN
OUT
OUT
USB
PCI-E
SYM 11 OF 19
PCIE_RCOMP
PCIE_IREF
RSVD
RSVD
PETP4
PETN4
PERP4
PERN4
PETP3
PETN3
PERP3
PERN3
PETP5_L3
PETN5_L3
PETP5_L2
PETN5_L2
PERP5_L2
PERN5_L2
PETP5_L1
PETN5_L1
PERP5_L1
PERN5_L1
USB2P7
USB2N7
PERP5_L3
PERN5_L3
PETP5_L0
PETN5_L0
PERP5_L0
PERN5_L0
OC1*/GPIO41
OC0*/GPIO40
OC2*/GPIO42
OC3*/GPIO43
RSVD
RSVD
USBRBIAS*
USBRBIAS
USB2N0
USB2P0
USB2N1
USB2P1
USB2N2
USB2P2
USB2N3
USB2P3
USB2N4
USB2P4
USB2N5
USB2P5
USB2N6
USB2P6
PERN1/USB3RN3
PERN2/USB3RN4
PERP1/USB3RP3
PERP2/USB3RP4
PETN1/USB3TN3
PETN2/USB3TN4
PETP1/USB3TP3
PETP2/USB3TP4
USB3RN1
USB3RN2
USB3RP1
USB3RP2
USB3TN1
USB3TN2
USB3TP1
USB3TP2
SYM 7 OF 19
LPC
SMBUS
SPI
C-LINK
SPI_IO3
SPI_MISO
SPI_IO2
SPI_CS2*
SPI_MOSI
SPI_CS0*
SPI_CS1*
LFRAME*
LAD2
LAD3
LAD1
SPI_CLK
LAD0
SMBALERT*/GPIO11
SMBCLK
SMBDATA
SML0ALERT*/GPIO60
SML0CLK
SML0DATA
SML1CLK_GPIO75
SML1ALERT*/PCHHOT*/GPIO73
SML1DATA/GPIO74
CL_CLK
CL_DATA
CL_RST*
BI
BI
IN
IN
OUT
OUT
IN
IN
OUT
OUT
OUT
OUT
IN
IN
OUT
OUT
IN
IN
OUT
OUT
IN
IN
NC
NC
OUT
OUT
IN
IN
OUT
IN
OUT
IN
IN
NC
NC
BI
IN
BI
BI
BI
BI
BI
OUT
BI
BI
OUT
BI
BI
BI
BI
OUT
OUT
OUT
OUT
IN
BI
BI
OUT
BI
OUT
BI
BI
IN
BI
BI
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZE
DRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
(IPU/IPD)
Ext A (SS)
Ext B (SS)
SML1ALERT# pull-up not provided on this
(IPU/IPD)
Reserved: Camera
USB Port Assignments:
page, may be wire-ORed into other signals.
Otherwise, 100k pull-up to 3.3V SUS required.
Thunderbolt lane 1
Camera
(& Ethernet if combo)
Thunderbolt lane 3
Thunderbolt lane 2
PCIe Port Assignments:
Thunderbolt lane 0
Reserved: FireWire
AirPort
Ext A (LS/FS/HS)
Ext B (LS/FS/HS)
BT
IR
(IPU/IPD)
(IPU)
(IPU)
(IPU)
(IPU)
(IPU)
(IPU)
(IPU)
(IPD)
SD Card Reader
(IPU)
USB3 Port Assignments:
Unused
Trackpad
Reserved: SD (HS)
25 71 81
1/20W
5% 201MF
100K
1/20W
5% 201MF
100K
14 16
14 16
14 16
40
14 16
25 71 81
14 71
BGA
2C+GT2
BROADWELL-ULT
CRITICAL
OMIT_TABLE
BGA
2C+GT2
BROADWELL-ULT
CRITICAL
OMIT_TABLE
36 71 74
36 71 74
25 71 81
25 71 81
25 71 81
25 71 81
25 71 81
25 71 81
25 71 81
25 71 81
66 74
66 74
66 71 74
66 71 74
34 81
34 81
34 71 81
34 71 81
66 71 81
66 71 81
66 71 81
66 71 81
1/20W
1%
201
MF
3.01K
PLACE_NEAR=U0500.A27:2.54mm
66 71 74
66 71 74
66 71 74
66 71 74
35 71 74
25 71 81
35 71 74
35 71 74
35 71 74
1/20W
1%
201
MF
22.6
PLACE_NEAR=U0500.AJ10:2.54mm
69
25 71 81
69
31 74
31 74
66 74
66 74
25 71 81
35 74
35 74
38 71 75
38 71 75
38 71 75
38 71 75
38 71 75
1/20W
5% 201MF
33
1/20W
5% 201MF
33
25 71 81
1/20W
5% 201MF
33
1/20W
5% 201MF
33
1/20W
5% 201MF
33
47 75
47 75
41 75
25 71 81
41 75
41 75
41 75
41 71 75
41 71 75
47 75
47 75
25 71 81
14 47 75
14 47 75
1/20W
5% 201MF
100K
1/20W
5% 201MF
1K
1/20W
5% 201MF
100K
1/20W
5% 201MF
1K
1/20W
5% 201MF
100K
1/20W
5% 201MF
100K
BOM_COST_GROUP=CPU
PCH PCIe,USB,LPC,SPI,SMBus
SYNC_DATE=10/23/2012
SYNC_MASTER=J41
USB3_EXTB_R2D_C_P
USB3_EXTB_D2R_P
USB3_EXTA_D2R_N
USB3_EXTA_D2R_P
USB3_EXTA_R2D_C_P
USB3_EXTB_D2R_N
PCH_USB_RBIAS
USB_IR_N
USB_BT_N
TP_USB_SDN
TP_USB_SDP
=PP3V3_SUS_PCH_VCC_SPI
XDP_USB_EXTA_OC_L
LPC_AD<2>
LPC_FRAME_L
LPC_AD<0>
LPC_AD<3>
=PP3V3_SUS_PCH_GPIO
PCH_SMBALERT_L
TP_CLINK_RESET_L
TP_CLINK_DATA
TP_CLINK_CLK
SML_PCH_1_DATA
PCH_SML1ALERT_L
SML_PCH_1_CLK
SML_PCH_0_DATA
SML_PCH_0_CLK
WOL_EN
LPC_AD_R<0>
SPI_CLK_R
LPC_AD_R<1>
LPC_AD_R<3>
LPC_AD_R<2>
LPC_FRAME_R_L
TP_SPI_CS1_L
SPI_CS0_R_L
SPI_MOSI_R
TP_SPI_CS2_L
SPI_IO<2>
SPI_MISO
SPI_IO<3>
XDP_USB_EXTC_OC_L
XDP_USB_EXTD_OC_L
XDP_USB_EXTB_OC_L
WOL_EN
SPI_IO<2>
SPI_IO<3>
PCIE_CAMERA_R2D_C_P
PCIE_CAMERA_R2D_C_N
USB3RPCIE_SD_R2D_C_N
PCIE_CAMERA_D2R_P
USB_IR_P
USB_EXTB_P
USB_EXTB_N
USB_EXTA_P
USB_EXTA_N
PCIE_TBT_D2R_N<0>
PCIE_TBT_D2R_P<0>
PCIE_TBT_R2D_C_N<0>
PCIE_TBT_R2D_C_P<0>
PCIE_TBT_D2R_N<3>
PCIE_TBT_D2R_N<1>
PCIE_TBT_D2R_P<1>
PCIE_TBT_R2D_C_N<1>
PCIE_TBT_R2D_C_P<1>
PCIE_TBT_D2R_N<2>
PCIE_TBT_D2R_P<2>
PCIE_TBT_R2D_C_N<2>
PCIE_TBT_R2D_C_P<2>
PCIE_TBT_R2D_C_N<3>
PCIE_AP_R2D_C_N
TP_PCIE_FW_D2RN
USB3RPCIE_SD_D2R_N
LPC_AD<1>
TP_PCIE_FW_D2RP
TP_PCIE_FW_R2D_CN
XDP_USB_EXTD_OC_L
PCH_SMBALERT_L
XDP_USB_EXTC_OC_L
XDP_USB_EXTB_OC_L
XDP_USB_EXTA_OC_L
PCH_PCIE_RCOMP
USB3_EXTA_R2D_C_N
PCIE_TBT_D2R_P<3>
PP1V05_S0SW_PCH_VCCUSB3PLL
PCIE_CAMERA_D2R_N
USB3RPCIE_SD_R2D_C_P
USB3RPCIE_SD_D2R_P
TP_PCIE_FW_R2D_CP
TP_USB_CAMERAP
TP_USB_CAMERAN
TP_USB_5P
TP_USB_5N
SMBUS_PCH_DATA
SMBUS_PCH_CLK
USB3_EXTB_R2D_C_N
USB_TPAD_P
PCIE_AP_R2D_C_P
PCIE_AP_D2R_P
PCIE_AP_D2R_N
PCIE_TBT_R2D_C_P<3>
USB_BT_P
USB_TPAD_N
R1500
1
2
R1570
1
2
R1543
1 2
R1542
1 2
R1544
1 2
R1540
1 2
R1541
1 2
R1591
1 2
R1549
1 2
R1590
1 2
R1548
1 2
R1582
1 2
R1583
1 2
R1580
1 2
R1581
1 2
U0500
AL3
AT1
AH2
AV3B27
A27
G17
F15
G11
F13
F10
F8
H10
E6
F17
G15
F11
G13
E10
E8
G10
F6
C30
B31
C29
B29
C23
B23
B21
B22
C31
A31
B30
A29
C22
A23
C21
A21
AM10
AN10
E13
E15
AN8
AR7
AR8
AR10
AM15
AM13
AP11
AR13
AM8
AT7
AP8
AT10
AL15
AN13
AN11
AP13
G20
E18
H20
F18
C33
B33
B34
A33
AJ11
AJ10
U0500
AF2
AD2
AF4
AU14
AW12
AY12
AW11
AV12
AN2
AP2
AH1
AL2
AN1
AK1
AU4
AU3
AH3
AA3
Y7
Y4
AC2
Y6
AF1
AA4
AA2
14 OF 82
15 OF 120
8.0.0
051-1573
dvt1
74
69
69
8
11 68
14 16
68
14
69
69
69
69
69
14 16
14 16
14 16
14 71
14 47 75
14 47 75
69
69
69
14
75
8
11
69
69
69
69
69
IN
OUT
BI
OUT
IN
IN
IN
IN
LPIO
GPIO
CPU/MISC
SYM 10 OF 19
SPKR/GPIO81
GPIO10
GPIO9
GPIO46
GPIO45
GPIO14
GPIO25
GPIO13
HSIOPC/GPIO71
GPIO50
GPIO49
GPIO48
GPIO44
GPIO47
GPIO59
GPIO58
GPIO57
GPIO56
GPIO26
GPIO27
GPIO28
GPIO24
GPIO16
GPIO17
GPIO15
LAN_PHY_PWR_CTRL/GPIO12
GPIO8
BMBUSY*/GPIO76
SDIO_D3/GPIO69
SDIO_D2/GPIO68
SDIO_D1/GPIO67
I2C0_SDA/GPIO4
UART1_TXD/GPIO1
UART1_CTS*/GPIO3
UART0_RTS*/GPIO93
UART0_CTS*/GPIO94
UART1_RXD/GPIO0
GSPI0_MOSI/GPIO86
GSPI1_CS*/GPIO87
GSPI1_CLK/GPIO88
GSPI0_CLK/GPIO84
GSPI0_MISO/GPIO85
GSPI0_CS*/GPIO83
RSVD
RSVD
PCH_OPI_COMP
RCIN*/GPIO82
SERIRQ
GSPI1_MISO/GPIO89
GSPI_MOSI/GPIO90
UART0_RXD/GPIO91
UART0_TXD/GPIO92
UART1_RST*/GPIO2
I2C1_SDA/GPIO6
I2C0_SCL/GPIO5
I2C1_SCL/GPIO7
SDIO_CLK/GPIO64
SDIO_CMD/GPIO65
SDIO_D0/GPIO66
SDIO_POWER_EN/GPIO70
DEVSLP0/GPIO33
DEVSLP1/GPIO38
DEVSLP2/GPIO39
THERMTRIP*
OUT
OUT
OUT
IN
OUT
OUT
BI
IN
OUT
OUT
OUT
IN
IN
IN
BI
BI
BI
NC
OUT
OUT
OUT
OUT
OUT
OUT
OUT
NC
OUT
BI
OUT
OUT
OUT
OUT
IN
OUT
OUT
IN
BI
BI
BI
IN
BI
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZE
DRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
BOM OPTIONS
BOM GROUP
TABLE_BOMGROUP_HEAD
TABLE_BOMGROUP_ITEM
R1616 should also be stuffed if
TBTLC for CR, S0 for RR
platform does not use SD card
Redwood Ridge: Alias to TBT_CIO_PLUG_EVENT_L, requires pull-up (S0).
Cactus Ridge: Alias to TBT_CIO_PLUG_EVENT, requires pull-down.
Pull-up/down on chipset support page (depends on TBT controller)
CR: TBT_GO2SX_BIDIR, requires 100k pull-up to SUS
(IPD-PLTRST#)
STUFFED R1632
GPIO12:
(IPD-DeepSx)
(IPD-PLTRST#)
(IPD)
RR/FR: DPHDMIMUX_SEL_TBT, requires 100k pull-up to TBTLC
(IPD)
(IPD-RSMRST#)
Requires connection to SMC via 1K series R
(IPD-PLTRST#)
Pull-up on TBT page
MF
1/20W
5% 201
10K
201
100K
1/20W
5% MF
5% 201
100K
1/20W
MF
5%
1/20W
100K
201MF
100K
1/20W
5% 201MF
MF 2015%
100K
1/20W
100K
1/20W
5% 201MF
100K
1/20W
5% 201MF
MF 2015%
1/20W
100K
100K
1/20W
5% 201MF
MF 2015%
1/20W
100K
1/20W
201
100K
MF
5%
201MF5%
1K
1/20W
MF 2015%
1/20W
100K
100K
1/20W
5%
MF
201
13 15 16 18
18
15 38 71
66
15 31
201
100K
MF
5%
1/20W
13 15 16 18
15 67
15 18
2015%
100K
MF
1/20W
2C+GT2
BROADWELL-ULT
CRITICAL
OMIT_TABLE
BGA
15 37 75
100K
MF
201
5%
1/20W
RAMCFG3:H
15 37 75
15 37 75
15 37 75
15 37
18 33
201
MF
5%
100K
1/20W
BAT54XV2T1
SOD-523
69
100K
MF
201
5%
1/20W
RAMCFG2:H
MF
5%
1M
1/20W
201
15 36 71
0201
1/20W
5%
0
MF
0
MF
0201
1/20W
5%
201
100K
MF
5%
1/20W
RAMCFG1:H RAMCFG0:H
5%
201
MF
100K
1/20W
26
15 71
15 65
15 71
65 71
40
15 16
15 16 18
15 16
15 32 64
15 71
15 66
15 25
15 16
15 16
15 18
15 63
15 47 71
15 18
15 32
15 31
32
15 38
15 66
39 75
15 16
15 16 18
15 16 18
15 16 18
18
15 16
5%
1K
1/20W
MF
201
1/20W
MF
100K
5% 201
MF
100K
1/20W
2015%
100K
MF5% 201
1/20W
5% MF
1/20W
100K
SD_ON_MLB
201
MF
1/20W
201
100K
5%
MF
1/20W
100K
5% 201
MF 201
100K
1/20W
5%
1/20W
MF 201
100K
5%
MF 201
1/20W
5%
100K
MF 2015%
100K
1/20W
201MF
100K
1/20W
5%
201
100K
5%
1/20W
MF
MF5%
100K
201
1/20W
201MF
100K
5%
1/20W
MF 2015%
1/20W
100K
201MF5%
1/20W
100K
201
1/20W
MF
100K
5%
1/20W
201MF
100K
5%
100K
201
1/20W
MF5%
5% MF
1/20W
100K
201
1/20W
5% MF 201
100K
10K
201
MF
1/20W
5%
MF5%
1/20W
201
100K
MF
1/20W
1%
49.9
201
PLACE_NEAR=U0500.AW15:2.54mm
201MF5%
1/20W
100K
100K
1/20W
5% 201MF
100K
MF
1/20W
5% 201
1/20W
5%
100K
MF 201
100K
MF
1/20W
5% 201
47K
1/20W
MF5% 201
5%
47K
MF
1/20W
201
MF
1/20W
5% 201
47K
201MF
1/20W
5%
47K
RAMCFG_SLOT
RAMCFG3:H,RAMCFG2:H,RAMCFG1:H,RAMCFG0:H
PCH GPIO/MISC/LPIO
SYNC_MASTER=J41 SYNC_DATE=01/19/2013
BOM_COST_GROUP=CPU
ENET_MEDIA_SENSE
=TBT_GO2SX_BIDIR
HDMI_TBT_MUX_SEL_GPIO12
PLT_RESET_L
PCH_GSPI0_CLK
BT_PWRRST_L
XDP_JTAG_ISP_TCK
TBT_PWR_EN
SD_PWR_EN
XDP_MLB_RAMCFG3
PCH_HSIO_PWR_EN
JTAG_TBT_TMS_PCH
PCH_TBT_PCIE_RESET_L
PCH_I2C1_SDA
PCH_STRP_TOPBLK_SWP_L
TBT_POC_RESET_L
PCH_I2C1_SCL
XDP_MLB_RAMCFG3
XDP_LPCPLUS_GPIO
XDP_PCH_GPIO17
TP_MEM_VDD_SEL_1V5_L
XDP_MLB_RAMCFG0
PCH_I2C0_SDA
PCH_UART1_TXD
PCH_UART1_CTS_L
JTAG_ISP_TDO
AP_RESET_L
PCH_UART1_RXD
PCH_GSPI0_MOSI
TPAD_SPI_CLK
PCH_GSPI0_CS_L
PCH_OPI_COMP
=TBT_CIO_PLUG_EVENT
PCH_UART1_RTS_L
PCH_I2C0_SCL
XDP_MLB_RAMCFG2
PCH_I2C0_SDA
PCH_I2C1_SCL
=PP1V05_S0_CPU_VCCST
XDP_MLB_RAMCFG0
PCH_UART1_RXD
PCH_UART1_RTS_L
PCH_I2C0_SCL
PCH_I2C1_SDA
PCH_UART1_CTS_L
PCH_UART1_TXD
HDMITBTMUX_FLAG_L
AP_S0IX_WAKE_L
TPAD_SPI_MOSI
TPAD_SPI_MISO
PCH_GSPI0_CS_L
PCH_GSPI0_MISO
PCH_GSPI0_MOSI
TPAD_SPI_CS_L
TPAD_SPI_CLK
XDP_MLB_RAMCFG1
HDMITBTMUX_FLAG_L
AP_S0IX_WAKE_L
TPAD_SPI_MISO
TPAD_SPI_CS_L
XDP_JTAG_ISP_TDI
SD_RESET_L
SMC_WAKE_SCI_L
TPAD_USB_IF_EN
LCD_PSR_EN
XDP_MLB_RAMCFG1
CAMERA_PWR_EN_PCH
HDD_PWR_EN
XDP_SDCONN_STATE_CHANGE_L
TPAD_SPI_INT_GPIO28_L
TPAD_SPI_INT_GPIO46_L
TPAD_SPI_INT_L
TPAD_SPI_INT_GPIO46_L
TPAD_SPI_MOSI
SSD_PWR_EN
TPAD_SPI_INT_GPIO28_L
=PP3V3_S0_PCH_GPIO
=PP3V3_S0_PCH_GPIO
TPAD_SPI_IF_EN
SPIROM_USE_MLB
JTAG_ISP_TDO
LPC_SERIRQ
LCD_PSR_EN
ENET_MEDIA_SENSE
BT_PWRRST_L
XDP_PCH_GPIO76
TPAD_SPI_IF_EN
PCH_GSPI0_MISO
PCH_GSPI0_CLK
LPC_SERIRQ
PM_THRMTRIP_L
PP3V3_S0_EDP_SW
LCD_IRQ_L
PLT_RESET_L
TBT_PWR_EN
PCH_HSIO_PWR_EN
AP_S0IX_WAKE_SEL
SSD_SR_EN_L
TPAD_SPI_INT_L
PCH_TCO_TIMER_DISABLE
XDP_MLB_RAMCFG2
XDP_PCH_GPIO76
XDP_LPCPLUS_GPIO
CAMERA_PWR_EN_PCH
SPIROM_USE_MLB
JTAG_TBT_TMS_PCH
XDP_JTAG_ISP_TDI
XDP_JTAG_ISP_TCK
SD_PWR_EN
XDP_SDCONN_STATE_CHANGE_L
TPAD_USB_IF_EN
SSD_PWR_EN
SD_RESET_L
XDP_PCH_GPIO17
=PP3V3_S5_PCH_GPIO
SMC_WAKE_SCI_L
AP_S0IX_WAKE_SEL
SSD_SR_EN_L
=PP3V3_S3RS4_PCH_GPIO
=PP3V3_S0RTBTLC_PCH_GPIO
HDD_PWR_EN
=PP3V3_S0_PCH_GPIO
=PP3V3_S3SW_SD_RESET
=PP3V3_S0_PCH_GPIO
SSD_RESET_L
CAM_PCIE_RESET_L
=PP3V3_S3RS0_CAMPWREN
=PP3V3_S3_PCH_GPIO
R1650
1
2
R1655
1
2
R1652
1 2
R1631
1
2
R1636
1
2
R1635
1
2
R1611
1
2
R1610
1 2
R1614
1 2
R1615
1 2
R1616
1 2
R1617
1 2
R1618
1 2
R1619
1 2
R1620
1 2
R1622
1 2
R1623
1 2
R1624
1 2
R1625
1 2
R1626
1 2
R1627
1 2
R1628
1 2
R1630
1 2
R1632
1 2
R1633
1 2
R1637
1 2
R1638
1 2
R1691
1 2
R1694
1 2
R1693
1 2
R1695
1 2
R1660
1 2
R1661
1 2
R1662
1 2
R1663
1 2
R1664
1 2
R1665
1 2
R1666
1 2
R1667
1 2
R1668
1 2
R1669
1 2
R1672
1 2
R1674
1 2
R1673
1 2
R1675
1 2
R1676
1 2
R1678
1 2
R1677
1 2
R1679
1 2
R1639
1
2
R1641
1 2
R1629
1 2
R1621
1
2
R1671
1
2
R1670
1 2
U0500
P1
P2
L2
N5
AM2
AT3
AH4
AD6
Y1
T3
AD5
AM4
AN3
AN5
AD7
AK4
AG5
AG3
AB6
U4
Y3
P3
AG6
AP1
AL4
AT5
AU2
AM3
L6
R6
N6
L8
L5
R7
N7
K2
Y2
F3
F2
F1
G4
AM7
AW15
V4
AB21
AF20
E3
F4
D3
E4
C3
E2
C4
T4
V2
D60
G1
J2
J1
K3
J4
J3
K4
G2
R1680
1
2
D1600
A K
R1600
1
2
R1682
1
2
R1681
1
2
16 OF 120
8.0.0
051-1573
dvt1
15 OF 82
15
15
15
15 16 18
15
15
15
15
15
15
75
15
15
15 16 18
15
15
6 8
16 17 55 68
15 16 18
15
15
15
15
15
15
15 67
15 31
15 37 75
15 37 75
15
15
15
15 37 75
15 37 75
15 16 18
15 37
15
15
15
15
12 13 15 18 26 65 68
12 13 15 18 26 65 68
15 18
15 38 71
15 65
15 71
15 71
15 37
15
15
41 65
15 25
15 63
15 36 71
15 16
15 16
15 18
15 47 71
15 18
15 16
15 16
15 66
15 16
15 37
15 32 64
15 66
15 16
13 68
15 38
15 31
15 32
68
68
15 71
12 13 15 18 26 65 68
68
12 13 15 18 26 65 68
18 44
68
IN
IN
IN
IN
IN
IN
IN
IN
OUT
OUT
IN
OUT
IN
OUT
OUT
IN
NC
NC
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
TP
TP
TP
TP
TP
TP
OUT
OUT
OUT
OUT
OUT
OUT
IN
OUT
IN
OUT
IN
IN
TP
OUT
IN
BI
OUT
TP
TP
BI
TP
BI
TP
BI
OUT
BI
IN
OUT
OUT
OUT
OUT
BI
IN
BI
IN
OUT
IN
OUT
BI
TP
IN
OUT
Y
NC NC
VCC
GND
A
NC
IN
NC
IN
TP
IN
TP
VER 3
D
S G
VER 3
D
S G
IN
VER 3
D
S G
VER 3
D
S G
IN
BI
IN
OUT
IN
IN
IN
IN
IN
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZE
DRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
PCH XDP Signals
OBSDATA_B0
OBSDATA_B2
NOTE: XDP_DBRESET_L pulled-up to 3.3V on PCH Support Page
Non-XDP Signals
NOTE: Should force PCH GPIO47 high to ensure TBT router powered to avoid leakage/clamping of signals.
These signals do not connect to XDP connector in this architecture, only accessible
via Top-Side Probe. Nets are listed here to show XDP associations and to make clear
what restrictions exist on PCH GPIOs when Top-Side Probe is used for PCH debug.
PCH/XDP Signals
USB Overcurrents are aliased, do not cause USB OC# events during PCH debug.
SDCONN_STATE_CHANGE_L is aliased, do not plug/unplug SD Cards during PCH debug.
VCC_OBS_AB
SSD_PCIEx_SEL_L straps are connected via 1K to common net.
LPCPLUS_GPIO is aliased, do not attempt use during PCH debug.
Unused & MLB_RAMCFGx GPIOs have TPs.
NOTE: Must not short XDP pins together!
TDI and TMS are terminated in CPU.
HOOK2
TDO
TRSTn
Merged (CPU/PCH) Micro2-XDP
OBSFN_D0
SCL
OBSDATA_A1
Use with 921-0133 Adapter Flex to
NOTE: This is not the standard XDP pinout.
TCK0
TCK1
SDA
HOOK1
OBSDATA_B3
PWRGD/HOOK0
OBSDATA_B1
OBSFN_B0
OBSDATA_A2
OBSDATA_A3
OBSFN_B1
OBSDATA_A0
ITPCLK/HOOK4
DBR#/HOOK7
OBSDATA_D3
ITPCLK#/HOOK5
OBSFN_D1
OBSDATA_D0
OBSDATA_C2
OBSDATA_C3
OBSDATA_C1
OBSFN_C1
OBSDATA_C0
OBSFN_C0
518S0847
support chipset debug.
Extra BPM Testpoints
RESET#/HOOK6
VCC_OBS_CD
OBSFN_A1
OBSFN_A0
CPU JTAG Isolation
JTAG_ISP (non-TMS) nets are aliased, do not attempt bit-banged JTAG during PCH debug.
XDP_PRESENT#
TMS
TDI
HOOK3
OBSDATA_D2
OBSDATA_D1
6
73
13 15 18
6
73
6
73
6
73
6
73
6
73
6
73
13 38 75
13 17 38 75
12 16 73
17 75
6
73
12 16 73
12 16 73
5% 201
1/20W
MF
XDP
1K
PLACE_NEAR=U0500.AG7:2.54mm
5% 201
1/20W
MF
XDP
51
PLACE_NEAR=U0500.E60:28mm
5%
0
402
MF-LF
XDP
1/16W
5%
0
0201
1/20W
MF
XDP
PLACE_NEAR=U5000.J3:2.54mm
5% 201
1/20W
MF
1K
XDP
PLACE_NEAR=U0500.C61:2.54mm
6
73
M-ST-SM1
CRITICAL
DF40RC-60DP-0.4V
XDP_CONN
6
73
6
73
6
73
6
73
6
73
6
73
6
73
6
73
6
73
6
73
TP-P6
TP-P6
TP-P6
TP-P6
TP-P6
TP-P6
8
5%
150
402
MF-LF
1/16W
5% 201
1/20W
MF
51
XDP
PLACE_NEAR=U0500.F62:28mm
12 16 73
5%
XDP
MF-LF
402
1/16W
1K
5% 201
1/20W
MF
51
PLACE_NEAR=U0500.AE62:28mm
NO STUFF
5% 201
1/20W
MF
51
XDP
PLACE_NEAR=U0500.AD62:28mm
5% 201
1/20W
MF
51
XDP
PLACE_NEAR=U0500.AD61:28mm
XDP
5% 201
1/20W
MF
51
PLACE_NEAR=U0500.AE61:28mm
5% 201
1/20W
MF
1K
PLACE_NEAR=U0500.AE63:28mm
NO STUFF
5%
0
0201
1/20W
MF
XDP
PLACE_NEAR=J1800.58:28mm
12 16 73
6
6
73
6
73
6
16 73
XDP
CERM-X5R
0201
6.3V
0.1UF
10%
15
14
14
6
73
66
TP-P6
14 35
15 18
14
TP-P6
XDP
CERM-X5R
0201
6.3V
0.1UF
10%
TP-P6
15 18
TP-P6
15 18
TP-P6
15 18
12
15
15 18
12
12
12
5% 201
1/20W
MF
1K
5% 201
1/20W
MF
1K
6
73
5% 201
1/20W
MF
1K
5% 201
1/20W
MF
1K
32
15
6
73
15
15 18
71
TP-P6
XDP
CERM-X5R
0201
6.3V
0.1UF
10%
0.1UF
CERM-X5R
0201
XDP
6.3V
10%
6
73
12 16
5% 201
1/20W
MF
PLACE_NEAR=U0500.AU62:28mm
NO STUFF
51
SOT891
74LVC1G07GF
16V
0201
X5R-CERM
0.1UF
10%
6
73
5%
201
1/20W
MF
330K
17 38 64
TP-P6
18
TP-P6
DMN5L06VK-7
SOT563
XDP
CRITICAL
SIGNAL_MODEL=DMN5L06VK_7
PLACE_NEAR=J1800.51:28mm
XDP
CRITICAL
SOT563
PLACE_NEAR=J1800.53:28mm
SIGNAL_MODEL=DMN5L06VK_7
DMN5L06VK-7
6
73
SOT563
SIGNAL_MODEL=DMN5L06VK_7
DMN5L06VK-7
XDP
CRITICAL
PLACE_NEAR=J1800.55:28mm
CRITICAL
PLACE_NEAR=J1800.57:28mm
XDP
SOT563
DMN5L06VK-7
SIGNAL_MODEL=DMN5L06VK_7
6
73
41
41
6
16 73
6
73
8
17 73
6
73
6
73
6
73
SYNC_MASTER=WFERRY_J43
CPU/PCH Merged XDP
SYNC_DATE=12/21/2012
BOM_COST_GROUP=CPU SUPPORT
CPU_CFG<19>
CPU_CFG<18>
CPU_CFG<15>
XDP_SYS_PWROK
XDP_CPU_TMS
CPU_CFG<11>
CPU_CFG<3>
CPU_CFG<12>
CPU_PWR_DEBUG
CPU_CFG<4>
ALL_SYS_PWRGD
XDP_PCH_TMS
XDP_PCH_TRST_L
XDP_CPU_TCK
XDP_BPM_L<6>
XDP_BPM_L<7>
XDP_BPM_L<5>
XDP_BPM_L<4>
XDP_BPM_L<3>
XDP_BPM_L<2>
PCH_JTAGX
XDP_PCH_TDI
XDP_CPU_TDO
XDP_PCH_TDO
=PP1V05_S0_CPU_VCCST
XDP_CPU_PRDY_L
XDP_CPU_PREQ_L
CPU_CFG<0>
CPU_CFG<2>
XDP_BPM_L<1>
CPU_CFG<5>
CPU_CFG<6>
CPU_CFG<7>
=SMBUS_XDP_SCL
XDP_PCH_TCK
CPU_VCCST_PWRGD
XDP_CPU_PWRBTN_L
PM_PWRBTN_L
PCH_JTAGX
PM_PCH_SYS_PWROK
CPU_CFG<17>
CPU_CFG<16>
CPU_CFG<8>
CPU_CFG<9>
CPU_CFG<13>
CPU_CFG<14>
XDP_CPURST_L
PLT_RESET_L
XDP_PCH_TRST_L
CPU_CFG<10>
XDP_PCH_TCK
XDP_CPU_VCCST_PWRGD
SSD_PCIE_SEL_L
USB_EXTA_OC_L
USB_EXTB_OC_L
SDCONN_STATE_CHANGE_L
JTAG_ISP_TCK
LPCPLUS_GPIO
XDP_MLB_RAMCFG0
XDP_USB_EXTC_OC_L
XDP_USB_EXTD_OC_L
XDP_MLB_RAMCFG1
XDP_SSD_PCIE1_SEL_L
XDP_PCH_GPIO76
=SMBUS_XDP_SDA
JTAG_ISP_TDI
XDP_SSD_PCIE0_SEL_L
XDP_SSD_PCIE2_SEL_L
XDP_PCH_GPIO17
XDP_SSD_PCIE3_SEL_L
XDP_MLB_RAMCFG3
XDP_MLB_RAMCFG2
=PP1V05_SUS_PCH_JTAG
XDP_CPU_TCK
XDP_CPU_TRST_L
XDP_CPU_TDO
XDP_TRST_L
XDP_PCH_TDO
=PP1V05_S0_XDP
XDP_BPM_L<0>
CPU_CFG<1>
XDP_CPU_TDI
XDP_CPU_PRESENT_L
XDP_PCH_TDI
XDP_JTAG_CPU_ISOL_L
XDP_PCH_TMS
XDP_DBRESET_L
=PP5V_S0_XDPJTAGISOL
=PP3V3_S5_XDPJTAGISOL
XDP_USB_EXTA_OC_L
MAKE_BASE=TRUE
XDP_USB_EXTB_OC_L
MAKE_BASE=TRUE
MAKE_BASE=TRUE
XDP_SDCONN_STATE_CHANGE_L
MAKE_BASE=TRUE
XDP_JTAG_ISP_TCK
MAKE_BASE=TRUE
XDP_JTAG_ISP_TDI
MAKE_BASE=TRUE
XDP_LPCPLUS_GPIO
MAKE_BASE=TRUE
XDP_CPUPCH_TRST_L
C1801
1
2
C1800
1
2
R1805
1 2
R1813
2 1
R1804
1 2
R1802
1 2
R1800
1 2
J1800
1
10
1112
1314
1516
1718
19
2
20
2122
2324
2526
2728
29
3
30
3132
3334
3536
3738
39
4
40
4142
4344
4546
4748
49
5
50
5152
5354
5556
5758
59
6
60
61
62
6364
78
9
TP1806
1
TP1807
1
TP1805
1
TP1804
1
TP1803
1
TP1802
1
R1830
1
2
R1810
1 2
R1831
1
2
R1896
2 1
R1892
2 1
R1891
2 1
R1890
2 1
R1899
2 1
R1835
1 2
TP1870
1
TP1874
1
TP1876
1
TP1877
1
TP1878
1
R1881
1 2
R1882
1 2
R1883
1 2
R1884
1 2
TP1887
1
C1804
1
2
C1806
1
2
R1897
2 1
U1845
2
3
1
5
6
4
C1845
1
2
R1845
1
2
TP1873
1
TP1886
1
Q1840
3
5
4
Q1840
6
2
1
Q1842
3
5
4
Q1842
6
2
1
16 OF 82
dvt1
051-1573
8.0.0
18 OF 120
75
12 16 73
12 16
6
16 73
12 16 73
12 16 73
6
16 73
12 16 73
6 8
15 17 55 68
75
12 16 73
73
68
73
68
68
68
73
OUT
OUT
OUT
IN
BIIN
OUT
IN
OUT
NC
NC
NC
OUT
IN
IN
NC
OUT
IN
NC
A Y
NC NC
VCC
GND
NC
IN
OUT
IN
IN
Y
A
B
08
Y
A
B
08
OUT
OUT
OUT
IN
OUT
IN
YA
B
NC
GND
VCC
32.768K
GND
THRM
VOUT
X2
X1
25M_A
25M_B
25M_C
VIOE_25M_A
VIOE_25M_B
VIOE_25M_C
VG3HOT
NC
VDD
PAD
NC
NC
NC
NC
VER 3
D
S G
VER 3
D
SG
DESCRIPTION
REFERENCE DES
BOM OPTION
QTY
PART NUMBER
CRITICAL
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZE
DRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
PCH uses HDA_SDO as a power-up strap. If low, ME functions normally.
If high, ME is disabled. This allows for full re-flashing of SPI ROM.
Q1920 & 5V pull-up allows circuit to work regardless of HDA voltage.
PCH ME Disable Strap
SMC controls strap enable to allow in-field control of strap setting.
PCH PWROK Generation
Must be powered if any VDDIO is powered.
This looks a little ugly to support
For SB RTC Power
to reduce VBAT draw.
+V3.3A should be first
create VDD_RTC_OUT.
internally ORed to
VBAT and +V3.3A are
Coin-Cell: VBAT (300-ohm & 10uF RC)
Coin-Cell & G3Hot: 3.42V G3Hot
GreenCLK 25MHz Power
Coin-Cell & No G3Hot: 3.3V S5
No Coin-Cell: 3.3V S5
No bypass necessary
PCH 24MHz Outputs
CAM XTAL Power
PCH Reset Button
IPD = 9-50k
VCCST (1.05V S0) PWRGD
Memory VTT Enable Level-Shifter
CPU output is on VDDQ rail (1.2V), TPS51916 has 1.8V Vih(min).
33uW when driven-low
Vih(min) = 1.8V
TPS51916 I(leak) = +/- 1uA,
WF: Do we need this?
available ~3.3V power
pin 5 must receive S5 power (Stuff R2042)
new and old parts. With GreenCLK Rev C
Chipset uses 24MHz crystal, GreenCLK kept to save 1x 25MHz crystal & 1x 32kHz crystal
No Coin-Cell: 3.42V G3Hot (no RC)
PCH 24MHz Crystal
NOTE: 30 PPM or better required for RTC accuracy
TBT XTAL Power
System RTC Power Source & 32kHz / 25MHz Clock Generator
12 75
25 74
6.3V
X5R
1UF
20%
0201
6.3V
20%
1UF
X5R
0201
25V
CERM
0201
12PF
5%
25V
CERM
0201
12PF
5%
38
201
1/20W
MF
22
PLACE_NEAR=U0500.AN15:5.1mm
5%
12 75
13 38 71 75 16 75
16V
0.1UF
X5R-CERM
10%
0201
MF
0
1/20W
0201
5%
NO STUFF
201
1/20W
MF
1M
5%
0
1/20W
MF
XDP
5%
0201
0
1/16W
MF-LF
SILK_PART=SYS RESET
NO STUFF
5%
402
201
1/20W
MF
10K
5%
201
1/20W
MF
100K
5%
1K
5%
201
1/20W
MF
12 75
38
0.1UF
10%
16V
X5R-CERM
0201
34 74
201
1/20W
MF
1M
5%
0
1/20W
MF
0201
5%
C0G
6.8PF
+/-0.1PF
25V
0201
6.8PF
C0G
+/-0.1PF
25V
0201
12 75
12 75
12
8
16 73
201
1/20W
MF
10K
5%
16V
X5R-CERM
10%
0.1UF
0201
13 18 38 64 66 71
201
1/20W
MF
330K
5%
SOT891
74AUP1G07GF
0.1UF
10%
16V
X5R-CERM
0201
6
57
26 27 38 39 75
16 17 38 64
74LVC2G08GT/S505
SOT833
BYPASS=U1950::5MM
X5R-CERM
10%
16V
0.1UF
0201
74LVC2G08GT/S505
CKPLUS_WAIVE=UNCONNECTED_PINS
SOT833
CKPLUS_WAIVE=UNCONNECTED_PINS
0
1/20W
MF
0201
5%
0
1/20W
MF
NO STUFF
0201
5%
1/20W
201
MF
1K
5%
13 16 38 75
13 75
13
0
1/20W
MF
NO STUFF
0201
5%
201
1/20W
MF
10K
5%
201
1/20W
MF
10K
5%
8
55
8
55
201
1/20W
MF
NO STUFF
100K
5%
74AUP1G09
SOT891
CRITICAL
SLG3NB148CV
CRITICAL
TQFN
CKPLUS_WAIVE=PwrTerm2Gnd
CRITICAL
3.20X2.50MM-SM1
24.000MHZ-20PPM-6PF
OMIT
CRITICAL
25.000MHZ-12PF-20PPM
SM-3.2X2.5MM
DMN5L06VK-7
SOT563
SIGNAL_MODEL=DMN5L06VK_7
SOT563
DMN5L06VK-7
SIGNAL_MODEL=DMN5L06VK_7
Chipset Support
SYNC_DATE=01/30/2013SYNC_MASTER=J41
BOM_COST_GROUP=CPU SUPPORT
197S0480
Y1905
1
XTAL,25MHZ,20PPM,12PF,3.2X2.5X.6MM,85C
CPU_VCCST_PWRGD
SPI_DESCRIPTOR_OVERRIDE
SPI_DESCRIPTOR_OVERRIDE_L
SYSCLK_CLK25M_X1
=PP3V3_S3RS0_SYSCLKGEN
LPC_CLK_SMC
=PPVDDIO_S3RS0_CAMCLK
SYSCLK_CLK25M_TBT
SYSCLK_CLK25M_CAMERA
SYSCLK_CLK25M_X2_R
=PPVRTC_G3_OUT
=PP3V3_S0_SB_PM
CPUVR_PGOOD_R
PM_PCH_APWROK
PM_S0_PGOOD
PM_PCH_SYS_PWROK
=DDRVTT_EN
=PP3V3_S0_MEM_VTTPWRCTL
=PP1V2_S3_MEM_VTTPWRCTL
=PP5V_S0_PCH_STRAP
SYS_PWROK_R
LPC_CLK24M_SMC_R
PCH_CLK24M_XTALOUT
HDA_SDOUT_R
=PP3V3_S0_SB_PM
PM_SYSRST_L
XDP_DBRESET_L
=PP3V42_G3H_CSPWRGD
CPUVR_PGOOD
CPU_VR_EN
ALL_SYS_PWRGD
SMC_DELAYED_PWRGD
=PP1V05_S0_CPU_VCCST
=PP3V3_S5_CSPWRGD
ALL_SYS_PWRGD
PCH_CLK24M_XTALOUT_R
=PPVBAT_G3H_SYSCLK
=PPVDDIO_TBTLC_CLK
PCH_CLK32K_RTCX1
PCH_CLK32K_RTCX2
=PP3V3_S5_SYSCLK
PM_SLP_S3_L
SYSCLK_CLK25M_X2
PCH_CLK24M_XTALIN
CPU_MEMVTT_PWR_EN_LSVDDQ
=PP3V3R1V5_S0SW_PCH_VCCSUSHDA
SPI_DESCRIPTOR_OVERRIDE_LS5V
MAKE_BASE=TRUE
CPU_VR_READY
MEMVTT_PWR_EN
MAKE_BASE=TRUE
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_RTC_CLK32K_RTCX2
LPC_CLK24M_SMC
MAKE_BASE=TRUE
PM_PCH_PWROK
MAKE_BASE=TRUE
C1902
1
2
C1910
1
2
C1905
12
C1906
1 2
R1927
1 2
C1924
1
2
R1905
1 2
R1906
1
2
R1996
1 2
R1997
1
2
R1995
1
2
R1920
1
2
R1921
1
2
C1922
1
2
R1916
1
2
R1915
1 2
C1915
1 2
C1916
1 2
R1931
1
2
C1930
1
2
R1970
1
2
U1970
2
3
1
5
6
4
C1970
1
2
U1950
1
2
4
8
7
C1950
1
2
U1950
5
6
4
8
3
R1963
2
1
R1960
2
1
R1962
1 2
R1951
1 2
R1950
1
2
R1955
1
2
R1961
1
2
U1930
2
1
3 6
4
U1900
9
8
15
12
7
10
16
17
5
13
11
6
14
1
4
3
Y1915
24
13
Y1905
2 4
1 3
Q1920
3
5
4
Q1920
6
2
1
dvt1
051-1573
8.0.0
19 OF 120
17 OF 82
5
2
74
18
33
74
68
17 68
75
68
68
68
75
17 68
68
6 8
15 16 55 68
68
16 17 38 64
75
68
68
18 68
74
8
11 63
71 75
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