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Samsung S3C6410 RISC Microprocessor User's Manual Rev1.20
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"s3c6410英文手册_v1.2,包含书签以便学习查阅"
三星的S3C6410是一款基于RISC(Reduced Instruction Set Computer)架构的微处理器,该处理器的手册版本为v1.20,发布日期为2009年2月13日。S3C6410主要针对嵌入式系统设计,广泛应用于移动设备、消费电子产品和工业控制等领域。
手册中详细介绍了S3C6410处理器的架构、功能特性、寄存器配置、接口规范以及编程模型等关键内容。以下是一些核心知识点:
1. **处理器架构**:S3C6410采用精简指令集,这种设计使得处理器能以较低的功耗实现高效运算。其内部可能包括多个处理核心,支持多任务并行处理,提高系统性能。
2. **RISC技术**:RISC技术强调减少指令集复杂性,通过优化指令执行效率来提升整体性能。S3C6410可能包含了一系列优化的指令,以实现快速执行常见操作。
3. **内存和接口**:手册会详细列出处理器的内存管理单元(MMU)、缓存结构以及各种外部接口如I/O端口、USB、以太网、SD卡接口等,这些都是嵌入式系统设计中的关键部分。
4. **寄存器配置**:每个处理器都有大量的寄存器用于控制和状态监控,手册会提供详细的寄存器描述,帮助开发者理解如何配置和使用它们。
5. **中断和异常处理**:S3C6410可能支持多种中断和异常处理机制,这些机制对于实时系统和响应外部事件至关重要。
6. **电源管理**:考虑到嵌入式设备的电池寿命,处理器通常具有节能模式和动态电压频率调整(DVFS)功能,手册会解释如何利用这些特性来优化能源使用。
7. **软件开发**:手册会提供编程模型和开发工具的指导,包括编译器选项、调试工具链以及如何编写高效的嵌入式代码。
8. **法律声明**:三星在手册中明确指出,购买半导体设备并不自动获得三星或其他公司的专利使用权,且不承担任何因产品应用或使用所产生的责任。
9. **版本更新**:三星保留随时改进产品或规格而不事先通知的权利,这意味着开发者需要关注最新的技术文档以获取最新信息。
S3C6410英文手册_v1.2是开发者和硬件工程师深入理解和开发基于S3C6410平台产品的关键参考资料,书签的添加更便于查找和学习相关章节。
xvi S3C6410X_USER’S MANUAL_REV 1.20
Table of Contents (Continued)
Chapter 14 Display Controller
14.4.5 Palette usage .................................................................................................................................14-16
14.4.5.1 Palette Configuration and Format Control..............................................................................14-16
14.4.6 Window Blending ...........................................................................................................................14-18
14.4.6.1 Overview.................................................................................................................................14-18
14.4.6.2 Blending Diagram/Details ...........................................................................................................14-20
14.4.7 COLOR-KEY Function...................................................................................................................14-22
14.4.8 VTIME CONTROLLER OPERATION ............................................................................................14-25
14.4.8.1 RGB Interface.........................................................................................................................14-25
14.4.8.2 I80 Interface Controller..........................................................................................................14-26
14.4.9 LDI Command Control ...................................................................................................................14-27
14.4.9.1 Auto Command.......................................................................................................................14-27
14.4.9.2 Normal Command ..................................................................................................................14-27
14.4.10 I80 CPU Interface Trigger............................................................................................................14-29
14.4.11 Interrupt........................................................................................................................................14-29
14.4.12 Virtual Display ..............................................................................................................................14-29
14.4.13 RGB Interface IO .........................................................................................................................14-31
14.4.14 LCD I80 INTERFACE IO..............................................................................................................14-32
14.4.14 ITU-R BT.601 INTERFACE IO.....................................................................................................14-33
14.4.15 LCD DaTA PiN MAP....................................................................................................................14-34
14.4.16 LCD NORMAL/BY-PASS MODE SELECTION ...........................................................................14-36
14.5 Programmer’s Model.............................................................................................................................14-37
14.5.1 Overview
........................................................................................................................................14-37
14.5.2 SFR Memory Map..........................................................................................................................14-37
14.6 Individual Register Descriptions............................................................................................................14-40
14.6.1 Video Main Control 0 Register.......................................................................................................14-40
14.6.2 Video Main Control 1 Register.......................................................................................................14-42
14.6.3 Video Main Control 2 Register.......................................................................................................14-43
14.6.4 VIDEO Time Control 0 Register.....................................................................................................14-43
14.6.5 Video Time Control 1 Register.......................................................................................................14-44
14.6.6 VIDEO Time Control 2 Register.....................................................................................................14-44
14.6.7 Window 0 Control Register ............................................................................................................14-44
14.6.8 Window 1 Control Register ...........................................................................................................14-46
14.6.9 Window 2 Control Register ............................................................................................................14-48
14.6.10 Window 3 Control Register ..........................................................................................................14-50
14.6.11 Window 4 Control Register ..........................................................................................................14-51
14.6.12 Window 0 Position Control A Register.........................................................................................14-52
14.6.13 Window 0 Position Control B Register.........................................................................................14-52
14.6.14 Window 0 Position Control C Register.........................................................................................14-52
14.6.15 Window 1 Position Control A Register.........................................................................................14-53
14.6.16 Window 1 Position Control B Register.........................................................................................14-53
14.6.17 Window 1 Position Control C Register........................................................................................14-54
14.6.18 Window 1 Position Control D Register
.........................................................................................14-54
14.6.19 Window 2 Position Control A Register.........................................................................................14-54
S3C6410X_USER’S MANUAL_REV 1.20 xvii
Table of Contents (Continued)
Chapter 14 Display Controller
14.6.20 Window 2 Position Control B Register ........................................................................................14-55
14.6.21 Window 2 Position Control C Register ........................................................................................14-55
14.6.22 Window 2 Position Control D Register ........................................................................................14-55
14.6.23 Window 3 Position Control A Register ........................................................................................14-56
14.6.24 Window 3 Position Control B Register ........................................................................................14-56
14.6.25 Window 3 Position Control C Register ........................................................................................14-57
14.6.26 Window 4 Position Control a Register.........................................................................................14-57
14.6.27 Window 4 Position Control B Register ........................................................................................14-58
14.6.28 Window 4 Position Control C Register ........................................................................................14-58
14.6.29 FRAME Buffer Address 0 Register..............................................................................................14-59
14.6.30 FRAME Buffer Address 1 Register..............................................................................................14-59
14.6.31 FRAME Buffer Address 2 Register..............................................................................................14-60
14.6.32 VIDEO interrupt Control 0 Register .............................................................................................14-60
14.6.33 VIDEO interrupt Control 1 Register .............................................................................................14-61
14.6.34 Win1 Color Key 0 Register ..........................................................................................................14-62
14.6.35 WIN 1 Color key 1 Register.........................................................................................................14-62
14.6.36 Win2 Color Key 0 Register ..........................................................................................................14-63
14.6.37 WIN2 Color key 1 Register..........................................................................................................14-63
14.6.38 Win3 Color Key 0 Register ..........................................................................................................14-64
14.6.39 WIN3 Color k
ey 1 Register..........................................................................................................14-64
14.6.40 Win4 Color Key 0 Register ..........................................................................................................14-65
14.6.41 WIN4 Color key 1 Register..........................................................................................................14-66
14.6.42 Dithering Control 1 Register ........................................................................................................14-67
14.6.43 WIN0 Color MAP .........................................................................................................................14-67
14.6.44 WIN1 Color MAP .........................................................................................................................14-68
14.6.44 WIN1 Color MAP .........................................................................................................................14-68
14.6.45 WIN2 Color MAP .........................................................................................................................14-68
14.6.46 WIN3 Color MAP .........................................................................................................................14-68
14.6.47 WIN4 Color MAP .........................................................................................................................14-69
14.6.48 Window Palette control Register .................................................................................................14-69
14.6.49 I80 / RGB Trigger Control Register .............................................................................................14-70
14.6.50 ITU 601 Interface control 0..........................................................................................................14-70
14.6.51 LCD I80 Interface Control 0.........................................................................................................14-71
14.6.52 LCD I80 Interface Control 1.........................................................................................................14-72
14.6.53 LCD I80 Interface Command Control 0.......................................................................................14-72
14.6.54 LCD I80 Interface Command Control 1.......................................................................................14-74
14.6.55 I80 System Interface Manual Command Control 0 .....................................................................14-74
14.6.56 I80 System Interface Manual Command Control 1 .....................................................................14-75
14.6.57 I80 System Interface Manual Command Control 2 .....................................................................14-75
14.6.58 LCD I80 Interfac
e Command.......................................................................................................14-76
14.6.59 Window 2’s Palette Data .............................................................................................................14-76
14.6.60 Window 3’s Palette Data .............................................................................................................14-77
14.6.61 Window 4’s Palette Data .............................................................................................................14-77
14.6.62 WIN0 Palette Ram Access Address (not SFR) ...........................................................................14-77
14.6.63 WIN1 Palette Ram Access Address (not SFR) ...........................................................................14-78
xviii S3C6410X_USER’S MANUAL_REV 1.20
Table of Contents (Continued)
Chapter 15 Post Processor
15.1 Overview................................................................................................................................................15-1
15.2 Features ................................................................................................................................................15-2
15.3 A Source and Destination Image Data Format .....................................................................................15-3
15.3.1 DMA Mode Operation ....................................................................................................................15-4
15.3.2 FIFO Mode Operation....................................................................................................................15-7
15.4 Image Size and Scale Ratio..................................................................................................................15-7
15.5 DMA operation of Source and Destination Image.................................................................................15-9
15.5.1 Start address..................................................................................................................................15-10
15.5.2 End address...................................................................................................................................15-10
15.6 Frame Management of POST Processor..............................................................................................15-12
15.6.1 Per Frame Management Mode......................................................................................................15-12
15.6.2 Free Run Mode ..............................................................................................................................15-12
15.7 Register File Lists..................................................................................................................................15-13
15.7.1 MODE Control Register .................................................................................................................15-15
15.7.3 Pre-Scale Image Size Register......................................................................................................15-17
15.7.4 Source Image Size Register ..........................................................................................................15-18
15.7.5 Horizontal Main Scale Ratio Register ............................................................................................15-18
15.7.6 Vertical Main Scale Ratio Register ................................................................................................15-18
15.7.7 Destination Image Size Register ...................................................................................................15-19
15.7.8 Pre-Scale Shift Factor Register .....................................................................................................15-19
15.7.9 DMA Start Address Register..........................................................................................................20
15.7.10 DMA End Addres
s Register.........................................................................................................15-21
15.7.11 Current Frame(Buffer0) and Next Frame(Buffer1) Offset Register .............................................15-22
15.7.12 Next Frame DMA Start Address Register....................................................................................15-23
15.7.13 Next Frame DMA End Address Register.....................................................................................15-24
15.7.14 DMA Start address Register for Output Cb and Cr .....................................................................15-24
15.7.15 DMA End Address Register for Output Cb and Cr ......................................................................15-25
15.7.16 Current Frame(Buffer0) and Next Frame(Buffer1) Offset Register for Output Cb and Cr ..........15-25
15.7.17 15.26 Next Frame DMA Start Address Register for Output Cb and Cr.......................................15-25
15.7.18 Next Frame DMA End Address Register for Output Cb and Cr ..................................................15-26
15.7.19 POSTENVID Register to Enable Video Processing ....................................................................15-26
15.7.20 MODE Control Register 2 ............................................................................................................15-27
S3C6410X_USER’S MANUAL_REV 1.20 xix
Table of Contents (Continued)
Chapter 16 TV Scaler
16.1 Overview ...............................................................................................................................................16-1
16.2 Features................................................................................................................................................16-2
16.3 A Source and Destination Image Data Format.....................................................................................16-3
16.3.1 DMA Mode Operation....................................................................................................................16-4
16.3.2 FIFO Mode Operation....................................................................................................................16-7
16.4 Image Size and Scale Ratio..................................................................................................................16-7
16.5 DMA operation of Source and Destination Image ................................................................................16-9
16.5.1 Start address .................................................................................................................................16-10
16.5.2 End address...................................................................................................................................16-10
16.6 Frame Management of TV Scaler.........................................................................................................16-12
16.6.1 Per Frame Management Mode......................................................................................................16-12
16.6.2 Free Run Mode..............................................................................................................................16-12
16.7 Register File Lists .................................................................................................................................16-13
16.7.1 MODE Control Register.................................................................................................................16-15
16.7.3 Pre-Scale Image Size Register .....................................................................................................16-17
16.7.4 Source Image Size Register..........................................................................................................16-18
16.7.5 Horizontal Main Scale Ratio Register............................................................................................ 16-18
16.7.6 Vertical Main Scale Ratio Register................................................................................................16-18
16.7.7 Destination Image Size Register ...................................................................................................16-19
16.7.8 Pre-Scale Shift Factor Register.....................................................................................................16-19
16.7.9 DMA Start Address Register .........................................................................................................16-20
16.7.10 DMA End Addres
s Register.........................................................................................................16-20
16.7.11 Current Frame (Buffer0) and Next Frame (Buffer1) Offset Register...........................................16-21
16.7.12 Next Frame DMA Start Address Register ...................................................................................16-21
16.7.13 Next Frame DMA End Address Register.....................................................................................16-22
16.7.14 DMA Start Address Register for Output Cb and Cr.....................................................................16-22
16.7.15 DMA End Address Register for Output Cb and Cr......................................................................16-23
16.7.16 Current Frame (Buffer0) and Next Frame (Buffer1) Offset Register for Output Cb and Cr ........16-23
16.7.17 Next Frame DMA Start Address Register for Output Cb and Cr.................................................16-23
16.7.18 Next Frame DMA End Address Register for Output Cb and Cr..................................................16-24
16.7.19 POSTENVID Register for Enable Video Processing...................................................................16-24
16.7.20 MODE Control Register 2............................................................................................................16-25
xx S3C6410X_USER’S MANUAL_REV 1.20
Table of Contents (Continued)
Chapter 17 TV Encoder
17.1 Overview................................................................................................................................................17-1
17.2 Feature ..................................................................................................................................................17-1
17.3 Block Diagram .......................................................................................................................................17-2
17.4 Functional Descriptions.........................................................................................................................17-3
17.4.1 Composition Of Analog Composite Signal.....................................................................................17-4
17.4.2 Common Ntsc System ...................................................................................................................17-5
17.4.3 Common Pal System .....................................................................................................................17-6
17.4.4 Composition Of Screen..................................................................................................................17-7
17.4.5 Requested Horizontal Timing ........................................................................................................17-8
17.4.6 Requested Vertical Timing.............................................................................................................17-9
17.5 Dac Board Configure Guide ..................................................................................................................17-10
17.6 Tv Encoder Register Summary .............................................................................................................17-11
17.7 Individual Register Descriptions............................................................................................................17-12
17.7.1 TVENCREG1 .................................................................................................................................17-12
17.7.2 TVENCREG2 .................................................................................................................................17-13
17.7.3 TVENCREG3 .................................................................................................................................17-13
17.7.4 TVENCREG4 .................................................................................................................................17-13
17.7.5 TVENCREG5 .................................................................................................................................17-14
17.7.6 TVENCREG6 .................................................................................................................................17-14
17.7.7 TVENCREG7 .................................................................................................................................17-14
17.7.8 TVENCREG8 .................................................................................................................................17-15
17.7.9 TVENCREG9 .................................................................................................................................17-15
17.7.10 TVENCREG10
.............................................................................................................................17-16
17.7.11 TVENCREG11 .............................................................................................................................17-16
17.7.12 TVENCREG12 .............................................................................................................................17-16
17.7.13 TVENCREG14 .............................................................................................................................17-17
17.7.14 TVENCREG15 .............................................................................................................................17-17
17.7.15 TVENCREG18 .............................................................................................................................17-19
17.7.16 TVENCREG19 .............................................................................................................................17-19
17.7.17 TVENCREG20 .............................................................................................................................17-20
17.7.18 TVENCREG21 .............................................................................................................................17-21
17.7.19 TVENCREG23 .............................................................................................................................17-21
17.7.20 TVENCREG25 .............................................................................................................................17-22
17.7.21 TVENCREG26 .............................................................................................................................17-23
17.7.22 TVENCREG27 .............................................................................................................................17-23
17.7.23 TVENCREG28 .............................................................................................................................17-24
17.7.24 TVENCREG29 .............................................................................................................................17-24
17.7.25 TVENCREG30 .............................................................................................................................17-24
17.7.26 TVENCREG31 .............................................................................................................................17-25
17.7.27 TVENCREG32 .............................................................................................................................17-25
17.7.28 TVENCREG33 .............................................................................................................................17-25
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