Insulation Specifications
PARAMETER TEST CONDITIONS
SPECIFICATIONS
UNIT
QSOP-16
IEC 60664-1
CLR External clearance
(1)
Side 1 to side 2 distance through air >3.7 mm
CPG External Creepage
(1)
Side 1 to side 2 distance across package
surface
>3.7 mm
DTI Distance through the insulation Minimum internal gap (internal clearance) 17 µm
CTI Comparative tracking index IEC 60112; UL 746A >600 V
Material Group According to IEC 60664-1 I
Overvoltage category per IEC 60664-1 Rated mains voltage ≤ 300 V
RMS
I-III
DIN V VDE V 0884-11:2017-01
(2)
V
IORM
Maximum repetitive peak isolation voltage AC voltage (bipolar) 566 V
PK
V
IOWM
Maximum isolation working voltage
AC voltage (sine wave); time-dependent
dielectric breakdown (TDDB) test; See TBD
400 V
RMS
DC voltage 566 V
DC
V
IOTM
Maximum transient isolation voltage
V
TEST
= V
IOTM
, t = 60 s (qualification); V
TEST
= 1.2 × V
IOTM
, t = 1 s (100% production)
4242 V
PK
V
IOSM
Maximum surge isolation voltage
(3)
Test method per IEC 62368-1, 1.2/50 µs
waveform, V
TEST
= 1.6 × V
IOSM
= 6400 V
PK
(qualification)
4000 V
PK
q
pd
Apparent charge
(4)
Method a: After I/O safety test subgroup 2/3,
V
ini
= V
IOTM
, t
ini
= 60 s; V
pd(m)
= 1.2 × V
IORM
,
t
m
= 10 s
≤ 5
pC
Method a: After environmental tests subgroup
1, V
ini
= V
IOTM
, t
ini
= 60 s;
V
pd(m)
= 1.6 × V
IORM
, t
m
= 10 s
≤ 5
Method b1: At routine test (100% production)
and preconditioning (type test), V
ini
= V
IOTM
,
t
ini
= 1 s;
V
pd(m)
= 1.875 × V
IORM
, t
m
= 1 s
≤ 5
C
IO
Barrier capacitance, input to output
(5)
V
IO
= 0.4 × sin (2 πft), f = 1 MHz ~1.5 pF
R
IO
Insulation resistance, input to output
(5)
V
IO
= 500 V, T
A
= 25°C > 10
12
ΩV
IO
= 500 V, 100°C ≤ T
A
≤ 150°C > 10
11
V
IO
= 500 V at T
S
= 150°C > 10
9
Pollution degree 2
Climatic category 55/125/21
UL 1577
V
ISO
Withstand isolation voltage
V
TEST
= V
ISO
, t = 60 s (qualification); V
TEST
=
1.2 × V
ISO
, t = 1 s (100% production)
3000 V
RMS
(1) Creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application.
Care should be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the
isolator on the printed-circuit board do not reduce this distance. Creepage and clearance on a printed-circuit board become equal
in certain cases. Techniques such as inserting grooves, ribs, or both on a printed circuit board are used to help increase these
specifications.
(2) This coupler is suitable for safe electrical insulation only within the safety ratings. Compliance with the safety ratings shall be ensured
by means of suitable protective circuits.
(3) Testing is carried out in air or oil to determine the intrinsic surge immunity of the isolation barrier.
(4) Apparent charge is electrical discharge caused by a partial discharge (pd).
(5) All pins on each side of the barrier tied together creating a two-pin device.
www.ti.com
ISO7041-Q1
SLLSFN3 – JUNE 2022
Copyright © 2022 Texas Instruments Incorporated
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Product Folder Links: ISO7041-Q1
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