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首页"TMS570LS3137芯片介绍及寄存器值详解"
"TMS570LS3137芯片介绍及寄存器值详解"
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更新于2024-03-22
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The TMS570LS3137 is a 16/32-bit RISC Flash Microcontroller from Texas Instruments, offering a robust and efficient solution for a wide range of embedded applications. This Technical Reference Manual provides in-depth information about the features and capabilities of the TMS570LS3137, including detailed descriptions of the chip architecture, memory layout, and peripheral interfaces.
The TMS570LS3137 features a high-performance ARM Cortex-R4F core with a maximum operating frequency of up to 180 MHz, making it suitable for demanding real-time applications. The chip also includes a variety of integrated peripherals, such as CAN, SPI, I2C, and GPIO interfaces, providing flexibility and scalability for different system requirements.
One of the key highlights of the TMS570LS3137 is its comprehensive set of on-chip safety mechanisms, such as ECC (Error Correction Code) for memory protection and hardware parity checks for CPU registers. These features enhance the reliability and robustness of the chip, making it ideal for safety-critical applications in industries such as automotive, industrial automation, and aerospace.
In addition to the technical details of the chip, this manual also includes a thorough description of the chip's register values and configurations. By understanding and utilizing these registers effectively, developers can leverage the full capabilities of the TMS570LS3137 and optimize the performance of their embedded systems.
Overall, the TMS570LS3137 is a versatile and powerful microcontroller that combines high performance, reliability, and safety features. With its rich set of features and comprehensive documentation, it is an ideal choice for developers looking to create advanced and secure embedded systems for a variety of applications.
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Contents
20.4.14 XOR Share Control Register (HETXOR)................................................................... 867
20.4.15 Request Enable Set Register (HETREQENS) ............................................................ 868
20.4.16 Request Enable Clear Register (HETREQENC).......................................................... 868
20.4.17 Request Destination Select Register (HETREQDS)...................................................... 869
20.4.18 NHET Direction Register (HETDIR) ........................................................................ 870
20.4.19 N2HET Data Input Register (HETDIN) ..................................................................... 871
20.4.20 N2HET Data Output Register (HETDOUT) ................................................................ 871
20.4.21 NHET Data Set Register (HETDSET) ...................................................................... 872
20.4.22 N2HET Data Clear Register (HETDCLR).................................................................. 872
20.4.23 N2HET Open Drain Register (HETPDR)................................................................... 873
20.4.24 N2HET Pull Disable Register (HETPULDIS) .............................................................. 873
20.4.25 N2HET Pull Select Register (HETPSL) .................................................................... 874
20.4.26 Parity Control Register (HETPCR).......................................................................... 875
20.4.27 Parity Address Register (HETPAR)......................................................................... 876
20.4.28 Parity Pin Register (HETPPR)............................................................................... 877
20.4.29 Suppression Filter Preload Register (HETSFPRLD) ..................................................... 878
20.4.30 Suppression Filter Enable Register (HETSFENA)........................................................ 878
20.4.31 Loop Back Pair Select Register (HETLBPSEL) ........................................................... 879
20.4.32 Loop Back Pair Direction Register (HETLBPDIR) ........................................................ 880
20.4.33 N2HET Pin Disable Register (HETPINDIS) ............................................................... 881
20.5 HWAG Registers.......................................................................................................... 882
20.5.1 HWAG Pin Select Register (HWAPINSEL) ................................................................. 883
20.5.2 HWAG Global Control Register 0 (HWAGCR0) ............................................................ 884
20.5.3 HWAG Global Control Register 1 (HWAGCR1) ............................................................ 884
20.5.4 HWAG Global Control Register 2 (HWAGCR2) ............................................................ 885
20.5.5 HWAG Interrupt Enable Set Register (HWAENASET) .................................................... 886
20.5.6 HWAG Interrupt Enable Clear Register (HWAENACLR).................................................. 887
20.5.7 HWAG Interrupt Level Set Register (HWALVLSET) ....................................................... 888
20.5.8 HWAG Interrupt Level Clear Register (HWALVLCLR) .................................................... 888
20.5.9 HWAG Interrupt Flag Register (HWAFLG).................................................................. 889
20.5.10 HWAG Interrupt Offset Register 0 (HWAOFF0) .......................................................... 890
20.5.11 HWAG Interrupt Offset Register 1 (HWAOFF1) .......................................................... 891
20.5.12 HWAG Angle Value Register (HWAACNT)................................................................ 892
20.5.13 HWAG Previous Tooth Period Value Register (HWAPCNT1) .......................................... 893
20.5.14 HWAG Current Tooth Period Value Register (HWAPCNT) ............................................. 893
20.5.15 HWAG Step Width Register (HWASTWD)................................................................. 894
20.5.16 HWAG Teeth Number Register (HWATHNB) ............................................................. 895
20.5.17 HWAG Current Teeth Number Register (HWATHVL).................................................... 895
20.5.18 HWAG Filter Register (HWAFIL)............................................................................ 896
20.5.19 HWAG Filter Register 2 (HWAFIL2) ........................................................................ 896
20.5.20 HWAG Angle Increment Register (HWAANGI) ........................................................... 897
20.6 Instruction Set ............................................................................................................. 898
20.6.1 Instruction Summary ........................................................................................... 898
20.6.2 Abbreviations, Encoding Formats and Bits ................................................................. 900
20.6.3 Instruction Description ......................................................................................... 903
21 High-End Timer Transfer Unit (HTU) Module ........................................................................ 969
21.1 Overview ................................................................................................................... 970
21.1.1 Features.......................................................................................................... 970
21.2 Module Operation......................................................................................................... 971
21.2.1 Data Transfers between Main RAM and N2HET RAM .................................................... 973
21.2.2 Arbitration of HTU Elements and Frames ................................................................... 977
21.2.3 Conditions for Frame Transfer Interruption.................................................................. 978
21.2.4 HTU Overload and Request Lost Detection................................................................. 978
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Contents
21.2.5 Memory Protection ............................................................................................. 981
21.2.6 Control Packet RAM Parity Checking........................................................................ 981
21.3 Use Cases ................................................................................................................. 983
21.3.1 Example: Single Element Transfer with One Trigger Request ........................................... 983
21.3.2 Example: Multiple Element Transfer with One Trigger Request.......................................... 983
21.3.3 Example: 64-Bit-Transfer of Control Field and Data Fields ............................................... 985
21.4 HTU Control Registers ................................................................................................... 986
21.4.1 Global Control Register (HTU GC) ........................................................................... 987
21.4.2 Control Packet Enable Register (HTU CPENA) ............................................................ 988
21.4.3 Control Packet (CP) Busy Register 0 (HTU BUSY0) ...................................................... 989
21.4.4 Control Packet (CP) Busy Register 1 (HTU BUSY1) ...................................................... 990
21.4.5 Control Packet (CP) Busy Register 2 (HTU BUSY2) ...................................................... 990
21.4.6 Control Packet (CP) Busy Register 3 (HTU BUSY3) ...................................................... 991
21.4.7 Active Control Packet and Error Register (HTU ACPE) ................................................... 991
21.4.8 Request Lost and Bus Error Control Register (HTU RLBECTRL) ....................................... 993
21.4.9 Buffer Full Interrupt Enable Set Register (HTU BFINTS).................................................. 994
21.4.10 Buffer Full Interrupt Enable Clear Register (HTU BFINTC) ............................................. 994
21.4.11 Interrupt Mapping Register (HTU INTMAP) ............................................................... 995
21.4.12 Interrupt Offset Register 0 (HTU INTOFF0) ............................................................... 996
21.4.13 Interrupt Offset Register 1 (HTU INTOFF1) ............................................................... 997
21.4.14 Buffer Initialization Mode Register (HTU BIM) ............................................................ 998
21.4.15 Request Lost Flag Register (HTU RLOSTFL) ........................................................... 1000
21.4.16 Buffer Full Interrupt Flag Register (HTU BFINTFL) ..................................................... 1000
21.4.17 BER Interrupt Flag Register (HTU BERINTFL).......................................................... 1001
21.4.18 Memory Protection 1 Start Address Register (HTU MP1S)............................................ 1002
21.4.19 Memory Protection 1 End Address Register (HTU MP1E)............................................. 1002
21.4.20 Debug Control Register (HTU DCTRL) ................................................................... 1003
21.4.21 Watch Point Register (HTU WPR) ........................................................................ 1004
21.4.22 Watch Mask Register (HTU WMR)........................................................................ 1004
21.4.23 Module Identification Register (HTU ID).................................................................. 1005
21.4.24 Parity Control Register (HTU PCR) ....................................................................... 1006
21.4.25 Parity Address Register (HTU PAR) ...................................................................... 1007
21.4.26 Memory Protection Control and Status Register (HTU MPCS)........................................ 1008
21.4.27 Memory Protection Start Address Register 0 (HTU MP0S)............................................ 1011
21.4.28 Memory Protection End Address Register (HTU MP0E) ............................................... 1011
21.5 Double Control Packet Configuration Memory ...................................................................... 1012
21.5.1 Initial Full Address A Register (HTU IFADDRA) .......................................................... 1013
21.5.2 Initial Full Address B Register (HTU IFADDRB) .......................................................... 1013
21.5.3 Initial N2HET Address and Control Register (HTU IHADDRCT) ....................................... 1014
21.5.4 Initial Transfer Count Register (HTU ITCOUNT).......................................................... 1015
21.5.5 Current Full Address A Register (HTU CFADDRA) ...................................................... 1016
21.5.6 Current Full Address B Register (HTU CFADDRB) ...................................................... 1017
21.5.7 Current Frame Count Register (HTU CFCOUNT) ........................................................ 1018
21.6 Examples ................................................................................................................. 1019
21.6.1 Application Examples for Setting the Transfer Modes of CP A and B of a DCP ..................... 1019
21.6.2 Software Example Sequence Assuming Circular Mode for Both CP A and B ........................ 1019
21.6.3 Example of an Interrupt Dispatch Flow for a Request Lost Interrupt................................... 1020
22 General-Purpose Input/Output (GIO) Module ...................................................................... 1021
22.1 Overview.................................................................................................................. 1022
22.2 Quick Start Guide ....................................................................................................... 1023
22.3 Functional Description of GIO Module................................................................................ 1025
22.3.1 I/O Functions................................................................................................... 1025
22.3.2 Interrupt Function ............................................................................................. 1026
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Contents
22.3.3 GIO Block Diagram ........................................................................................... 1026
22.4 Device Modes of Operation............................................................................................ 1028
22.4.1 Emulation Mode ............................................................................................... 1028
22.4.2 Power-Down Mode (Low-Power Mode) .................................................................... 1028
22.5 GIO Control Registers .................................................................................................. 1029
22.5.1 GIO Global Control Register (GIOGCR0).................................................................. 1030
22.5.2 GIO Interrupt Detect Register (GIOINTDET) .............................................................. 1031
22.5.3 GIO Interrupt Polarity Register (GIOPOL) ................................................................. 1032
22.5.4 GIO Interrupt Enable Registers (GIOENASET and GIOENACLR) ..................................... 1033
22.5.5 GIO Interrupt Priority Registers (GIOLVLSET and GIOLVLCLR)....................................... 1035
22.5.6 GIO Interrupt Flag Register (GIOFLG) ..................................................................... 1038
22.5.7 GIO Offset Register 1 (GIOOFF1) .......................................................................... 1039
22.5.8 GIO Offset B Register (GIOOFF2).......................................................................... 1040
22.5.9 GIO Emulation A Register (GIOEMU1) .................................................................... 1041
22.5.10 GIO Emulation B Register (GIOEMU2) ................................................................... 1042
22.5.11 GIO Data Direction Registers (GIODIR[A-B])............................................................ 1043
22.5.12 GIO Data Input Registers (GIODIN[A-B])................................................................. 1043
22.5.13 GIO Data Output Registers (GIODOUT[A-B]) ........................................................... 1044
22.5.14 GIO Data Set Registers (GIODSET[A-B]) ................................................................ 1044
22.5.15 GIO Data Clear Registers (GIODCLR[A-B]) ............................................................. 1045
22.5.16 GIO Open Drain Registers (GIOPDR[A-B]) .............................................................. 1045
22.5.17 GIO Pull Disable Registers (GIOPULDIS[A-B]).......................................................... 1046
22.5.18 GIO Pull Select Registers (GIOPSL[A-B])................................................................ 1046
22.6 I/O Control Summary ................................................................................................... 1047
23 FlexRay Module .............................................................................................................. 1048
23.1 Overview.................................................................................................................. 1049
23.1.1 Feature List .................................................................................................... 1049
23.2 FlexRay Module Block Diagram....................................................................................... 1050
23.3 FlexRay Module Block Mapping....................................................................................... 1053
23.4 Transfer Unit Block Diagram........................................................................................... 1054
23.5 Transfer Unit Functional Description.................................................................................. 1055
23.5.1 Transfer Control ............................................................................................... 1057
23.5.2 Transfer Configuration RAM ................................................................................. 1063
23.5.3 Memory Protection Mechanism ............................................................................. 1063
23.6 Communication Cycle .................................................................................................. 1064
23.6.1 Static Segment ................................................................................................ 1064
23.6.2 Dynamic Segment............................................................................................. 1064
23.6.3 Symbol Window ............................................................................................... 1064
23.6.4 Network Idle Time (NIT)...................................................................................... 1065
23.6.5 Configuration of NIT Start and Offset Correction Start................................................... 1065
23.7 Communication Modes ................................................................................................. 1065
23.7.1 Time-Triggered Distributed (TT-D).......................................................................... 1065
23.8 Clock Synchronization .................................................................................................. 1066
23.8.1 Global Time .................................................................................................... 1066
23.8.2 Local Time ..................................................................................................... 1066
23.8.3 Synchronization Process ..................................................................................... 1066
23.8.4 Sync Frame Transmission ................................................................................... 1067
23.8.5 External Clock Synchronization ............................................................................. 1067
23.9 Error Handling ........................................................................................................... 1067
23.9.1 Clock Correction Failed Counter ............................................................................ 1068
23.9.2 Passive to Active Counter.................................................................................... 1068
23.9.3 HALT Command............................................................................................... 1068
23.9.4 FREEZE Command........................................................................................... 1068
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Contents
23.10 Communication Controller States..................................................................................... 1069
23.10.1 Communication Controller State Diagram................................................................ 1069
23.10.2 DEFAULT_CONFIG State.................................................................................. 1070
23.10.3 CONFIG State................................................................................................ 1070
23.10.4 MONITOR_MODE........................................................................................... 1071
23.10.5 READY State................................................................................................. 1071
23.10.6 WAKEUP State .............................................................................................. 1072
23.10.7 STARTUP State ............................................................................................. 1075
23.10.8 NORMAL_ACTIVE State ................................................................................... 1080
23.10.9 NORMAL_PASSIVE State ................................................................................. 1080
23.10.10 HALT State.................................................................................................. 1080
23.11 Network Management .................................................................................................. 1081
23.12 Filtering and Masking................................................................................................... 1081
23.12.1 Slot Counter Filtering........................................................................................ 1082
23.12.2 Cycle Counter Filtering...................................................................................... 1082
23.12.3 Channel ID Filtering ......................................................................................... 1083
23.12.4 FIFO Filtering................................................................................................. 1083
23.13 Transmit Process ....................................................................................................... 1083
23.13.1 Static Segment............................................................................................... 1083
23.13.2 Dynamic Segment ........................................................................................... 1083
23.13.3 Transmit Buffers ............................................................................................. 1084
23.13.4 Frame Transmission......................................................................................... 1085
23.13.5 Null Frame Transmission ................................................................................... 1085
23.14 Receive Process ........................................................................................................ 1085
23.14.1 Dedicated Receive Buffers ................................................................................. 1085
23.14.2 Frame Reception ............................................................................................ 1086
23.14.3 Null Frame Reception ....................................................................................... 1086
23.15 FIFO Function ........................................................................................................... 1086
23.15.1 Description.................................................................................................... 1086
23.15.2 Configuration of the FIFO................................................................................... 1088
23.15.3 Access to the FIFO .......................................................................................... 1088
23.16 Message Handling ...................................................................................................... 1088
23.16.1 Reconfiguration of Message Buffers ...................................................................... 1088
23.16.2 Host Access to Message RAM............................................................................. 1089
23.16.3 FlexRay Protocol Controller Access to Message RAM ................................................. 1094
23.17 Module RAMs ........................................................................................................... 1095
23.17.1 Message RAM ............................................................................................... 1096
23.17.2 Parity Check.................................................................................................. 1099
23.18 Interrupts ................................................................................................................. 1103
23.18.1 Transfer Unit Interrupts ..................................................................................... 1103
23.18.2 Communication Controller Interrupts...................................................................... 1105
23.19 FlexRay Module Registers............................................................................................. 1108
23.19.1 Transfer Unit Registers ..................................................................................... 1108
23.19.2 Communication Controller Registers...................................................................... 1155
23.20 Minimum Peripheral Clock Frequency .............................................................................. 1242
23.21 Assignment of FlexRay Configuration Parameters ................................................................ 1243
23.22 Emulation/Debug Support ............................................................................................. 1244
24 Controller Area Network (DCAN) Module............................................................................ 1245
24.1 Overview.................................................................................................................. 1246
24.1.1 Features ........................................................................................................ 1246
24.1.2 Functional Description ........................................................................................ 1246
24.2 CAN Blocks .............................................................................................................. 1247
24.2.1 CAN Core ...................................................................................................... 1247
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Contents
24.2.2 Message RAM ................................................................................................. 1247
24.2.3 Message Handler ............................................................................................. 1247
24.2.4 Message RAM Interface...................................................................................... 1248
24.2.5 Register and Message Object Access ..................................................................... 1248
24.2.6 Dual Clock Source ............................................................................................ 1248
24.3 CAN Bit Timing .......................................................................................................... 1249
24.3.1 Bit Time and Bit Rate ......................................................................................... 1249
24.3.2 DCAN Bit Timing Registers .................................................................................. 1251
24.4 CAN Module Configuration............................................................................................. 1253
24.4.1 DCAN RAM Initialization through Hardware............................................................... 1253
24.4.2 CAN Module Initialization .................................................................................... 1253
24.5 Message RAM ........................................................................................................... 1255
24.5.1 Structure of Message Objects ............................................................................... 1255
24.5.2 Addressing Message Objects in RAM...................................................................... 1257
24.5.3 Message RAM Representation in Debug/Suspend Mode ............................................... 1258
24.5.4 Message RAM Representation in Direct Access Mode .................................................. 1258
24.6 Message Interface Register Sets ..................................................................................... 1259
24.6.1 Message Interface Register Sets 1 and 2 ................................................................. 1259
24.6.2 Using Message Interface Register Sets 1 and 2.......................................................... 1260
24.6.3 Message Interface Register 3 ............................................................................... 1261
24.7 Message Object Configurations ....................................................................................... 1262
24.7.1 Configuration of a Transmit Object for Data Frames ..................................................... 1262
24.7.2 Configuration of a Transmit Object for Remote Frames ................................................. 1262
24.7.3 Configuration of a Single Receive Object for Data Frames ............................................. 1262
24.7.4 Configuration of a Single Receive Object for Remote Frames.......................................... 1263
24.7.5 Configuration of a FIFO Buffer .............................................................................. 1263
24.7.6 Reconfiguration of Message Objects for the Reception of Frames..................................... 1263
24.7.7 Reconfiguration of Message Objects for the Transmission of Frames................................. 1263
24.8 Message Handling ...................................................................................................... 1264
24.8.1 Message Handler Overview ................................................................................. 1264
24.8.2 Receive/Transmit Priority..................................................................................... 1264
24.8.3 Transmission of Messages in Event Driven CAN Communication ..................................... 1265
24.8.4 Updating a Transmit Object.................................................................................. 1265
24.8.5 Changing a Transmit Object ................................................................................. 1265
24.8.6 Acceptance Filtering of Received Messages .............................................................. 1266
24.8.7 Reception of Data Frames ................................................................................... 1266
24.8.8 Reception of Remote Frames ............................................................................... 1266
24.8.9 Reading Received Messages ............................................................................... 1266
24.8.10 Requesting New Data for a Receive Object............................................................. 1267
24.8.11 Storing Received Messages in FIFO Buffers ............................................................ 1267
24.8.12 Reading from a FIFO Buffer............................................................................... 1267
24.9 CAN Message Transfer ................................................................................................ 1269
24.9.1 Automatic Retransmission ................................................................................... 1269
24.9.2 Auto-Bus-On ................................................................................................... 1270
24.10 Interrupt Functionality .................................................................................................. 1270
24.10.1 Message Object Interrupts ................................................................................. 1270
24.10.2 Status Change Interrupts ................................................................................... 1271
24.10.3 Error Interrupts ............................................................................................... 1271
24.11 Global Power-Down Mode............................................................................................. 1272
24.11.1 Entering Global Power-Down Mode....................................................................... 1272
24.11.2 Wakeup From Global Power-Down Mode................................................................ 1272
24.12 Local Power-Down Mode .............................................................................................. 1273
24.12.1 Entering Local Power-Down Mode ........................................................................ 1273
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