PHY Interface for PCI Express, SATA, USB 3.1, DisplayPort, and Converged IO Architectures,
ver 5.1
©2007-2018 Intel Corporation – All rights reserved Page 18 of 161
Some key features of the SATA PHY are:
• Standard PHY interface enables multiple IP sources for SATA controllers and provides a
target interface for SATA PHY vendors.
• Supports 1.5 GT/s only or 1.5 GT/s and 3.0 GT/s, or 1.5 GT/s, 3.0 GT/s and 6.0 GT/s serial
data transmission rate
• Utilizes 8-bit, 16-bit, or 32-bit parallel interface to transmit and receive SATA data
• Allows integration of high speed components into a single functional block as seen by the
device designer
• Data and clock recovery from serial stream on the SATA bus
• Holding registers to stage transmit and receive data
• 8b/10b encode/decode and error indication
• COMINIT and COMRESET transmission and reception
2.5 Low Pin Count Interface and SerDes Architecture
To address the issue of increasing signal count, the message bus interface was introduced in PIPE
4.4 and utilized for PCIe lane margining at the receiver and elastic buffer depth control. In PIPE
5.0, all legacy PIPE signals without critical timing requirements were mapped into message bus
registers so that their associated functionality could be accessed via the message bus interface
instead of implementing dedicated signals. Any new features added in PIPE 4.4 and onwards are
available only via message bus accesses unless they have critical timing requirements that need
dedicated signals.
To facilitate the design of general purpose PHYs delivered as hard IPs and to provide the MAC
with more freedom to do latency optimizations, a SerDes architecture was defined in PIPE 5.0.
This architecture simplifies the PHY and shifts much of the protocol specific logic into the MAC.
To maximize interoperability between MAC and PHY IPs, PHY designs must adhere to the
requirements stated in Table 2-1 for support of the legacy pin interface versus the low pin count
interface and for support of the original PIPE architecture versus the SerDes architecture.
The legacy pin interface refers to a pin interface that utilizes all the applicable dedicated signals
as well as the message bus interface for features not supported through dedicated signals. The
low pin count interface refers to a pin interface that utilizes the message bus interface for all
features supported through the message bus, using dedicated signals only for features not
supported through the message bus. The legacy pin interface dedicated signals are defined in
PIPE 4.4.1 and earlier and have been deprecated in PIPE 5.0.
The original PIPE architecture is represented in Figure 4-2, Figure 4-3, Figure 4-4 and Figure 4-5.
The SerDes Architecture is represented in Figure 4-7 and Figure 4-8.
The legacy pin interface and the low pin count interface are not simultaneously operational, with
the exception of PCIe 4.0 lane margining at the receiver being controlled via the low pin count
interface while other operations are managed over the legacy interface. A PHY must be statically
configured to utilize either the low pin count interface or the legacy pin interface, e.g. no dynamic
switching between the interfaces based on operational rate is permitted. Finally, a SerDes
architecture datapath must always utilize the low pin count interface; using the legacy pin
interface with SerDes architecture is considered illegal.
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