I2C SPEC 2.1更新：简化设计与制造商指南

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本资源是关于"I2C规格标准"的详细指南，版本为2.1，发布于2000年1月，由Philips Semiconductors编写。I2C（Inter-Integrated Circuit）是一种串行通信接口，特别适合于在微控制器和其他电子设备之间传输数据，因其简单、高效和低功耗而被广泛采用。 **1. 版本更新与购买信息** 该文档首先概述了规格的三个主要版本：1.0（1992）、2.0（1983）和2.1（1999），强调了每个版本的改进和特点。同时，它也提到了如何通过购买Philips I2C-bus组件来获取最新规格支持。 **2. I2C的优势** 章节2着重介绍了I2C的优点，对设计者而言，它提供了易用性、灵活的地址寻址方式以及低成本的解决方案。制造商则可以受益于其简化的设计过程和高效的通信能力，从而降低成本并提高产品性能。 **3. I2C概念介绍** 接下来部分详细阐述了I2C的基本概念，包括数据的串行传输方式，START和STOP条件在数据交换中的作用，以及数据的有效性和验证规则。 **4-8. 传输细节** 这部分深入讲解了I2C的数据传输机制，包括字节格式、确认信号的处理，以及同步和仲裁过程，确保数据在多设备连接时的正确传输。 **9. 7位地址模式** 7位地址模式的定义和使用在此处详述，如第一字节中地址位的解释，包括通用呼叫地址、START字节以及与CBUS兼容性的考虑。 **10-13. 扩展模式** 文档还涵盖了两种扩展模式：Fast模式和High Speed (Hs)模式。Fast模式提高了数据传输速率，而Hs模式进一步提升了速度，并介绍了相应的数据传输格式和切换机制，使得I2C能在更高速度下保持可靠通信。总结来说，这份I2C Spec 2.1版本提供了全面的I2C协议规范，包括基础原理、数据传输流程、地址识别方法和性能提升策略，对于任何使用或设计I2C系统的工程师来说，都是一个不可或缺的参考资料。通过理解这些内容，设计师和制造商能够有效地集成和优化I2C通信，以满足不同应用的需求。

Philips Semiconductors

The I

C-bus specification

Generation of clock signals on the I

C-bus is always the

responsibility of master devices; each master generates its

own clock signals when transferring data on the bus. Bus

clock signals from a master can only be altered when they

are stretched by a slow-slave device holding-down the

clock line, or by another master when arbitration occurs.

5 GENERAL CHARACTERISTICS

Both SDA and SCL are bi-directional lines, connected to a

positive supply voltage via a current-source or pull-up

resistor (see Fig.3). When the bus is free, both lines are

HIGH. The output stages of devices connected to the bus

must have an open-drain or open-collector to perform the

wired-AND function. Data on the I

C-bus can be

transferred at rates of up to 100 kbit/s in the

Standard-mode, up to 400 kbit/s in the Fast-mode, or up to

3.4 Mbit/s in the High-speed mode. The number of

interfaces connected to the bus is solely dependent on the

bus capacitance limit of 400 pF. For information on

High-speed mode master devices, see Section 13.

6 BIT TRANSFER

Due to the variety of different technology devices (CMOS,

NMOS, bipolar) which can be connected to the I

C-bus,

the levels of the logical ‘0’ (LOW) and ‘1’ (HIGH) are not

fixed and depend on the associated level of V

(see

Section 15 for electrical specifications). One clock pulse is

generated for each data bit transferred.

6.1 Data validity

The data on the SDA line must be stable during the HIGH

period of the clock. The HIGH or LOW state of the data line

can only change when the clock signal on the SCL line is

LOW (see Fig.4).

Fig.3 Connection of Standard- and Fast-mode devices to the I

C-bus.

MBC631

SCLKN1

OUT

SCLK

DATAN1

OUT

DATA

DEVICE 1

SDA (Serial Data Line)

SCL (Serial Clock Line)

SCLKN2

OUT

SCLK

DATAN2

OUT

DATA

DEVICE 2

pull-up

resistors

Philips Semiconductors

The I

C-bus specification

7 TRANSFERRING DATA

7.1 Byte format

Every byte put on the SDA line must be 8-bits long. The

number of bytes that can be transmitted per transfer is

unrestricted. Each byte has to be followed by an

acknowledge bit. Data is transferred with the most

significant bit (MSB) first (see Fig.6). If a slave can’t

receive or transmit another complete byte of data until it

has performed some other function, for example servicing

an internal interrupt, it can hold the clock line SCL LOW to

force the master into a wait state. Data transfer then

continues when the slave is ready for another byte of data

and releases clock line SCL.

In some cases, it’s permitted to use a different format from

the I

C-bus format (for CBUS compatible devices for

example). A message which starts with such an address

can be terminated by generation of a STOP condition,

even during the transmission of a byte. In this case, no

acknowledge is generated (see Section 10.1.3).

7.2 Acknowledge

Data transfer with acknowledge is obligatory. The

acknowledge-related clock pulse is generated by the

master. The transmitter releases the SDA line (HIGH)

during the acknowledge clock pulse.

The receiver must pull down the SDA line during the

acknowledge clock pulse so that it remains stable LOW

during the HIGH period of this clock pulse (see Fig.7). Of

course, set-up and hold times (specified in Section 15)

must also be taken into account.

Usually, a receiver which has been addressed is obliged to

generate an acknowledge after each byte has been

received, except when the message starts with a CBUS

address (see Section 10.1.3).

When a slave doesn’t acknowledge the slave address (for

example, it’s unable to receive or transmit because it’s

performing some real-time function), the data line must be

left HIGH by the slave. The master can then generate

either a STOP condition to abort the transfer, or a repeated

START condition to start a new transfer.

If a slave-receiver does acknowledge the slave address

but, some time later in the transfer cannot receive any

more data bytes, the master must again abort the transfer.

This is indicated by the slave generating the

not-acknowledge on the first byte to follow. The slave

leaves the data line HIGH and the master generates a

STOP or a repeated START condition.

If a master-receiver is involved in a transfer, it must signal

the end of data to the slave- transmitter by not generating

an acknowledge on the last byte that was clocked out of

the slave. The slave-transmitter must release the data line

to allow the master to generate a STOP or repeated

START condition.

Fig.6 Data transfer on the I

C-bus.

handbook, full pagewidth

MSC608

SDA

SCL

STOP or

repeated START

condition

START or

repeated START

condition

1 2 3 - 8 9

ACK

7812

MSB

acknowledgement

signal from slave

byte complete,

interrupt within slave

clock line held low while

interrupts are serviced

acknowledgement

signal from receiver

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