开关电容Σ-Δ调制器的精确建模

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"1646 IEEETRANSACTIONSONINSTRUMENTATIONANDMEASUREMENT,VOL.54,NO.4,AUGUST2005 ModelingofSwitched-CapacitorDelta–Sigma ModulatorsinSIMULINK HashemZare-Hoseini,IzzetKale,andOmidShoaei,Member,IEEE" 本文详细探讨了开关电容Σ-Δ调制器在SIMULINK中的建模方法。Σ-Δ调制器是一种常用的模拟数字转换器（ADC），它利用过采样和噪声整形技术来提高信噪比和降低量化噪声。开关电容电路是Σ-Δ调制器的核心组成部分，它们通过开关元件和电容实现信号的积分和采样。首先，文章强调了精确的行为建模，包括考虑开关和运算放大器的热噪声。这些噪声源对Σ-Δ调制器的性能有显著影响，尤其是在低频和高频下的噪声表现。开关噪声主要源于开关器件的随机开关动作，而运算放大器的热噪声则与温度和带宽有关。其次，作者还讨论了时钟抖动的影响。时钟抖动会引入额外的相位不确定性，这可能会影响信号的转换精度，特别是在高速Σ-Δ调制器中。接下来，非理想因素如积分器的有限直流增益（DCG）和单位增益带宽、速度限制、DCG非线性以及输入寄生电容也被纳入模型。这些非理想特性使得实际的Σ-Δ调制器在性能上与理想模型存在差距。特别地，论文指出，积分器的DCG非线性是许多建模尝试中被忽视的一个关键参数。这种非线性会导致调制器行为的显著低估，增加输出噪声地板并恶化谐波失真。通过分析和建模这个参数，可以更准确地预测调制器的实际行为。此外，论文还涉及了量化器的磁滞效应，开关的时钟馈通，以及电荷注入等其他重要因素。这些效应都会影响Σ-Δ调制器的动态性能和输出质量。为了验证所提出的模型，作者进行了详尽的行为模拟，这些模拟结果接近于晶体管级的仿真，从而证明了模型的有效性和准确性。通过这种方式，设计者可以在设计阶段就评估Σ-Δ调制器的性能，避免在硬件实现后出现意料之外的问题。这篇论文为开关电容Σ-Δ调制器的系统级建模提供了一个全面的框架，对于理解和优化这类调制器的设计至关重要，特别是对于那些在信号处理、通信和测量应用中依赖高精度模拟数字转换的领域。

1646 IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT, VOL. 54, NO. 4, AUGUST 2005

Modeling of Switched-Capacitor Delta–Sigma

Modulators in SIMULINK

Hashem Zare-Hoseini, Izzet Kale, and Omid Shoaei, Member, IEEE

Abstract—Precise behavioral modeling of switched-capacitor

modulators is presented. Considering noise (switches’ and

op-amps’ thermal noise), clock jitter, nonidealities of integrators

and op-amps including ﬁnite dc-gain (DCG) and unity gain band-

width, slew-limiting, DCG nonlinearities and the input parasitic

capacitance, quantizer hysteresis, switches’ clock-feedthrough,

and charge injection, exhaustive behavioral simulations that are

close models of the transistor-level ones can be performed. The

DCG nonlinearity of the integrators, which is not considered in

many

modulators’ modeling attempts, is analyzed, estimated,

and modeled. It is shown that neglecting this parameter would

lead to a signiﬁcant underestimation of the modulators’ behavior

and increase the noise ﬂoor as well as the harmonic distortion

at the output of the modulator. Evaluation and validation of the

models were done via behavioral and transistor-level simulations

for a second-order modulator using SIMULINK and HSPICE

with a generic 0.35-

m CMOS technology. The effects of the

nonidealities and nonlinearities are clearly seen when compared

to the ideal modulator in the behavioral and actual modulator in

the circuit-level environment.

Index Terms—Charge injection, clock feedthrough, correlated

double sampling, delta–sigma modulators, hysteresis, nonideality,

nonlinearity, SIMULINK, switched capacitor.

I. INTRODUCTION

MONG the oversampling converters, ones have

achieved the most attraction recently in high-resolution

applications due to their noise shaping behavior that leads

them to inherent superior linearity, simple realization, and low

sensitivity to circuit imperfections [1]. Such converters reduce

the need for complex analog circuit implementation and, due to

their oversampling nature, act as the most suitable architectures

for accurate low to moderately high frequency applications.

modulators can be realized in either the continuous-time

(CT) or switched-capacitor (SC) approach. While CT modula-

tors have the advantages of lower power consumption, higher

speed, and intrinsic anti-aliasing ﬁltering, they suffer from the

difﬁculty of designing, sensitivity to clock jitter, and also excess

loop delay [2]. As far as the implementation technique is con-

cerned, SC modulators are preferred to CT modulators because

they can be more efﬁciently realized in standard CMOS tech-

nology [1], [3]. Moreover, they provide a highly controllable

Manuscript received June 15, 2004; revised April 15, 2005.

H. Zare-Hoseini and I. Kale are with the Applied DSP and VLSI Research

Group, Department of Electronic Systems, University of Westminster, London,

W1W 6UW, U.K. (e-mail: h.zhoseini@wmin.ac.uk)

O. Shoaei is with the IC Design Laboratory, Electrical and Computer Engi-

neering Department, University of Tehran, Tehran, Iran.

Digital Object Identiﬁer 10.1109/TIM.2005.851085

design as well as being more robust to clock jitter and feed-

back delay problems. In this paper, the SC

modulators are

considered.

Although

modulators have relatively straightforward

realizations, the appropriate architecture selection, including

single loop or MASH, loop ﬁlter type, order and coefﬁcients,

and the number of bits of the quantizer, would be a difﬁcult

task. Also, the requirements of the building blocks such as

integrators’ bandwidth, dc-gain (DCG), slew rate and output

swings, the quantizer threshold, the digital-to-analog con-

verter (DAC), the switches, and the clock and power supply

accuracy cannot be easily estimated. Several techniques have

been used for time-domain analysis of these modulators listed

and discussed brieﬂy in [3], such as SPICE, SWITCAP, and

table-lookup models. For instance, the SPICE simulations are

precise, but they take extremely long times especially for very

high-resolution narrow-band modulators because of both long

period cycles and the high accuracy needed. Hence, choosing

the optimized architecture and estimating the requirements of

building blocks is a very time-consuming procedure in tran-

sistor-level design and simulation (SPICE). There is a need for

a time-efﬁcient and accurate simulation environment. To this

effect, the user friendly, versatile SIMULINK tool was chosen

to develop detailed models of the modulators’ building blocks.

The popular SIMULINK simulator proved to be an excellent

time-efﬁcient candidate for this initial task.

In this paper, detailed analytical models of the basic building

blocks (integrators and op-amps) and also the nonidealities of

a typical modulator are presented, followed by SIMULINK

models of them. Most previous

modulator models have

not considered the effect of DCG nonlinearity in integrators,

leading to a signiﬁcant underestimation of the modulators’ be-

havior and harmonic distortion. In this paper, this is analyzed,

estimated, and modeled in SIMULINK, as well as other blocks

of a typical

modulator. Moreover, several behavioral and

transistor-level simulations were performed in SIMULINK

and HSPICE using a generic 0.35-

m CMOS technology to

validate the analyses and models. Since in the ﬁrst stage of very

high-resolution modulators correlated-double-sampled (CDS)

integrators are routinely used to attenuate the effect of offset

and ﬂicker noise, for comparison purposes, both typical and

CDS integrators are discussed in this paper.

In Section II, the integrator characteristics such as ﬁnite

DCG, nonlinear DCG, and settling behavior are presented.

Section III presents noise contributors such as sampling and

op-amp thermal noise. Switch nonidealities are considered next

following with a discussion about clock jitter. In Section VI, a

brief review of quantizer nonidealities are discussed. Then the

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